Lead Digital Verification Engineer
Mount Royal, SKCadence
Candidates need an engineering degree in electrical, computer or computer science, plus understanding of verification methodologies such as UVM and metric-driven verification. Strong problem-solving skills, English communication and experience with SystemVerilog assertions are required.
SystemVerilog, UVM, Python, Perl, Ruby, Cadence tools
Lead Digital Verification Engineer
Mount Royal, SKCadence
Candidates need an engineering degree in electrical, computer or computer science, plus understanding of verification methodologies such as UVM and metric-driven verification. Strong problem-solving skills, English communication and experience with SystemVerilog assertions are required.
SystemVerilog, UVM, Python, Perl, Ruby, Cadence tools
Principal Analog IC Designer
Toronto, ON +1Cadence
5+ YOECandidates need at least 5 years of CMOS SerDes or high-speed I/O experience, a strong grasp of jitter and signal equalization, and proficiency with circuit simulation CAD tools. An MS or PhD in EE is required.
Cadence