FY27 Intern - Camera HW ASIC Verification Intern - Canada (12 or 16 months)
Vancouver, BCQualcomm Canada ULC
1+ YOECandidates need Verilog or SystemVerilog skills, ASIC design verification experience and scripting ability. Study toward a bachelor's degree in electrical, computer or a related engineering field is required.
Verilog, UVM, Python, Perl
FY27 Intern - Camera Design Implementation Intern - Canada (16 months)
Vancouver, BCQualcomm Canada ULC
Candidates need to be enrolled in a bachelor's degree in engineering, computer science or a related field, with an expected graduation of November 2028 or later. Strong scripting skills and knowledge of ASIC design flow are needed.
synthesis tools, static timing analysis tools, formal verification tools
Camera Design Engineer
Vancouver, BCQualcomm Canada ULC
3+ YOECandidates need a bachelor's, master's or PhD in a computer, electrical or related engineering field, with 4 to 2 years of hardware or related experience depending on degree. Verilog or VHDL RTL design, design verification and bus protocol experience are key.
Verilog, VHDL, TCL, Perl, Python
ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a Bachelor's degree in engineering, science or a related field and 2+ years of ASIC design or verification work, or a new-grad co-op, internship or PEY background. Preferred skills include SystemVerilog, UVM, Verilog or VHDL, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python
ASICS Design Verification Engineer (Vancouver, Markham OR Remote)
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in engineering or science and 2+ years of ASIC design or verification experience. Preferred skills include SystemVerilog and UVM testbench development, RTL design, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python