“AHB” jobs in Canada

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• 2d

  FY27 Intern - Display IP FPGA Emulation Intern - Canada (4 months)

  Markham, ON

  On-siteInternship

  QC

  Qualcomm Canada ULC

  1+ YOECandidates need to be in study toward a bachelor's degree in computer engineering, engineering science, computer science or a related field, with at least one year of academic programming experience. Knowledge of RTL, Verilog or SystemVerilog, digital design and Linux is required, plus teamwork and communication skills.

  FPGA, Verilog, Linux, Perl, Python, TCL

  6d

  Firmware Engineer, Edge AI Silicon Validation (Embedded C)

  Markham, ON

  On-site

  QC

  Qualcomm Canada ULC

  2+ YOECandidates need at least 2 years of embedded firmware or silicon validation experience in C, plus a bachelor's degree and 4 or more years of ASIC validation work (or a master's with 3 years, or a PhD with 2 years). Strong debugging, lab equipment and communication skills are needed.

  Oscilloscope, Protocol analyzer, JTAG debugger, FPGA prototyping system, Perforce, Git

  6d

  Sr ASIC Design Verification Engineer, Low Power AI

  Markham, ON

  On-site

  QC

  Qualcomm Canada ULC

  2+ YOEQualcomm Canada ULC needs candidates with a bachelor's, master's or PhD and 2 to 4+ years of ASIC work, depending on degree. Expert skill in Verilog, SystemVerilog, UVM and C, plus a deep understanding of ASIC/VLSI concepts, is required.

  SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl

  6d

  FY27 Intern - Display IP Engineering Internship - Canada (16 months)

  Markham, ON

  On-siteInternship

  QC

  Qualcomm Canada ULC

  1+ YOECandidates need to be enrolled in a bachelor's program in electrical, computer or engineering science, or a related field, with a graduation date of November 2028 or later. They need programming experience in C, C++ or Python, knowledge of RTL, Verilog or SystemVerilog and digital design, and good communication and teamwork skills.

  Verilog, VHDL, Perl, Python, TCL, GNU Make

  6d

  SOC Design Engineer

  Markham, ON +2

  On-site

  QC

  Qualcomm Canada ULC

  4+ YOECandidates need a degree in science or engineering and 4+ years of ASIC design, verification or integration work, with strong digital front-end design skills in Verilog, SystemVerilog and VHDL. Experience with power domains, clock domain crossing, low-power design and chip design tools is needed.

  Spyglass, Design Compiler, Cadence LEC, Perl, TCL

  6d

  Camera Design Engineer

  Vancouver, BC

  On-site

  QC

  Qualcomm Canada ULC

  3+ YOECandidates need a bachelor's, master's or PhD in a computer, electrical or related engineering field, with 4 to 2 years of hardware or related experience depending on degree. Verilog or VHDL RTL design, design verification and bus protocol experience are key.

  Verilog, VHDL, TCL, Perl, Python

  27d

  Staff ASIC Verification Engineer, Low Power AI

  Markham, ON

  On-site

  QC

  Qualcomm Canada ULC

  4+ YOEQualcomm Canada ULC needs candidates with a relevant degree and 4+ years of ASIC work (3+ with a master's, 2+ with a PhD). Expert knowledge of Verilog, VHDL and SystemVerilog UVM is required, plus solid C skills.

  SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl

• 6d

  SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)

  Markham, ON

  On-site

  QT

  Qualcomm Technologies, Inc.

  7+ YOEQualcomm needs a candidate with 7+ years of silicon validation or platform bring-up experience and deep knowledge of NoCs, AXI, memory hierarchy, power modes and debug. A degree in engineering or computer science is required, with embedded C/C++, Python and assembly skills.

  JTAG debugger, Perfmon, kernel debugger, emulation platform

  6d

  SoC Infrastructure/NoC, Power & Performance Validation Engineer

  Markham, ON

  On-site

  QT

  Qualcomm Technologies, Inc.

  5+ YOECandidates need several years of ASIC design, validation or verification experience, with a strong grasp of on-chip interconnects, performance and power. Strong programming in C, C++, Python and assembly, plus JTAG and kernel debugging, are expected.

  JTAG debuggers, kernel debuggers, state dump scripts, Python, C, C++

• 10d

  SoC Design Engineer

  Burnaby, BC

  $86k–$186k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  10+ YOECandidates need a bachelor's degree in electrical, electronics, computer engineering, computer science or physics, plus 10 or more years in semiconductor or electronic design. Strong analytical, communication and cross-functional collaboration skills are expected, and experience with SoC, ASIC, FPGA or mixed-signal design, and on-chip protocols, is preferred.

  EDA tools

• 14d

  RTL Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong Verilog and SystemVerilog skills, scripting experience, and knowledge of AXI, AHB and AMBA protocols. Experience with ASIC design flows and processor or security subsystems is preferred.

  Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

  17d

  RTL Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in electrical or computer engineering or a related field, with strong Verilog and SystemVerilog skills and knowledge of CPU and embedded processor architectures. Experience with AXI, AHB, AMBA and ASIC design tools is preferred.

  Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

  28d

  Sr. Manager - RTL Design Manager

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a proven record of engineering leadership and IP or RTL team management. They need strong Verilog/SystemVerilog skills, knowledge of ASIC design flows and a Bachelor's degree in engineering or computer science.

  Verilog, SystemVerilog, AMBA, AXI, AHB

  28d

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's in computer or electrical engineering, and strong Verilog or SystemVerilog RTL design skills. Experience delivering ASIC or FPGA products, plus networking or high-speed interface knowledge, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

• 15d

  RTL Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  AMD needs candidates with a Bachelor's or Master's degree in an electrical, computer or related engineering field, with Master's preferred. Strong skills in Verilog, SystemVerilog and scripting such as Python, Tcl or Perl are expected, along with knowledge of processor subsystems and ASIC design flows.

  Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

  17d

  RTL Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a strong background in RTL design, Verilog and SystemVerilog, and scripting in Python, Tcl, Perl, Ruby, or Make. Experience with AXI, AHB, AMBA protocols, ASIC design tools, and a Bachelor's or Master's degree in electrical or computer engineering are expected.

  Verilog, SystemVerilog, C-DPI, FPGA, ASIC simulation and synthesis tools

  23d

  RTL Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a Bachelor's or Master's degree in electrical or computer engineering, computer science or a related field, with Verilog and SystemVerilog skills, scripting experience, and knowledge of bus protocols such as AXI and AHB. Experience with ASIC design tools and CPU or microprocessor subsystem architecture is preferred.

  Verilog, Tcl, Ruby, Perl, Python, Makefile

  23d

  Silicon Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a bachelor's degree in electrical or computer engineering, with a master's or PhD preferred. AMD wants hands-on ASIC firmware and hardware verification experience with UVM, SystemVerilog, C/C++ and bus protocols such as AXI and AHB.

  UVM, Verilog, C-DPI, Python, Perl, Make

  23d

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

  23d

  Sr. Manager - RTL Design Manager

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  AMD needs a leader with experience managing IP or RTL design teams and strong Verilog/SystemVerilog skills. Candidates should know RTL microarchitecture, ASIC verification flows and on-chip protocols such as AXI and AHB, and hold a bachelor's degree in an engineering or computer discipline.

  Verilog, SystemVerilog

• 20d

  RTL Design Engineer - AI Tools

  Toronto, ON

  $100–$175/hr

  

  Mercor

  3+ YOECandidates need 3 to 10 years of digital RTL design or design verification experience, strong Verilog, SystemVerilog and UVM skills, and solid digital design fundamentals. Experience with ASIC design flows and EDA tools is also required.

  Verilog, SystemVerilog, UVM, EDA tools

  20d

  Design Verification Engineer - Fully Remote | Upto $175/hr

  Toronto, ON

  $100–$175/hr

  

  Mercor

  3+ YOECandidates need 3 to 10 years of digital RTL design or design verification experience, strong Verilog/SystemVerilog and UVM skills, and solid knowledge of digital design fundamentals. They also need ASIC design flow experience and the ability to write clear design documentation.

  Verilog, SystemVerilog, UVM, EDA tools

• 22d

  Staff Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  9+ YOECandidates need a Bachelor's or Master's in computer science, electrical engineering or a related field, plus at least 9 years of ASIC design verification experience. Strong SystemVerilog and UVM skills and advanced debugging are required.

  SystemVerilog, UVM, EDA tools

  22d

  Senior Staff ASIC Design Egineer - AI/ML Hardware IP

  Toronto, ON

  T

  Talentlab

  6+ YOECandidates need six or more years of ASIC design and integration experience (or a Master's plus five years, or a PhD plus four), strong Verilog/SystemVerilog skills, and experience owning complex SoC blocks. A Bachelor's, Master's or PhD in electrical engineering or a related field is required, and the candidate must be legally authorized to work in Canada.

  Verilog, SystemVerilog, VCS, Verdi, Questa, Xcelium

7 companies