Senior Emulation Performance Methodology & Debug Engineer
Markham, ONQualcomm Technologies, Inc.
4+ YOECandidates need a bachelor's, master's or PhD in a science or engineering field with 4+, 3+ or 2+ years of ASIC design or verification experience respectively. Preferred: 5+ years in emulation and silicon environments, plus Verilog/SystemVerilog, C, Python, TCL and FPGA timing closure skills.
Veloce, Palladium, FPGA prototyping, JTAG debugger, Xilinx FPGA, Intel FPGA
SoC Debug Engineer, Senior Staff
Markham, ONQualcomm Technologies, Inc.
9+ YOECandidates need 9+ years of pre-silicon and post-silicon bring-up and debug experience, RTL understanding, and hands-on use of JTAG and lab equipment such as logic analyzers and oscilloscopes. A Master's in Computer or Electrical Engineering is required, along with the stated years of ASIC design or validation experience.
JTAG, Logic analyzer, Signal generator
SoC Debug Engineer, Staff
Markham, ONQualcomm Technologies, Inc.
6+ YOECandidates need 6+ years of pre-silicon and post-silicon bring-up and failure analysis experience, plus RTL understanding and JTAG and lab equipment skills. A Master's in Computer or Electrical Engineering is required, along with ASIC experience.
JTAG, Logic analyzer, Signal generator