Senior ASIC Design Engineer - DSP/Analog/SerDes
Ottawa, ONCC
Celero Communications, Inc.
10+ YOECandidates need a master's or PhD in electrical or computer engineering, 10+ years of digital ASIC design, and strong Verilog or SystemVerilog skills. Knowledge of DSP, high-speed SerDes, mixed-signal or optical communications is also required.
Verilog, SystemVerilog, Python, Tcl, MATLAB, UVM