“RTL simulation tools” jobs in Canada – Page 2

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• 17d

  Hardware Designer

  Remote in Canada

  $95k–$145k/yrRemoteFull Time

  

  Fidus Systems: Founded in 2001, Fidus Systems is a premier electronic system design and development company with specialized expertise in FPGA design, embedded…

  5+ YOECandidates need at least 5 years of electronics design experience and a degree in electrical or computer engineering. Strong knowledge of high-speed circuits, multi-layer PCB design and high-speed protocols such as PCIe, DDR4 and USB-C is required.

  OrCAD Capture CIS, Cadence Allegro, LTSpice, oscilloscope, VNA, signal generator

• 17d

  RTL Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a strong background in RTL design, Verilog and SystemVerilog, and scripting in Python, Tcl, Perl, Ruby, or Make. Experience with AXI, AHB, AMBA protocols, ASIC design tools, and a Bachelor's or Master's degree in electrical or computer engineering are expected.

  Verilog, SystemVerilog, C-DPI, FPGA, ASIC simulation and synthesis tools

  22d

  GPU Design Verification Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need IP-level ASIC verification experience, UVM testbench skills, and knowledge of SystemVerilog, Verilog, C/C++ and scripting in Python, Perl or shell. A Bachelor's or Master's in computer or electrical engineering is preferred.

  UVM, Verilog, C++, Python, Perl, Makefile

  23d

  Firmware Engineering Manager

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a background in semiconductor firmware or embedded systems, with engineering management experience and a record of building teams. Deep GFX/SOC architecture and debug skills, plus hands-on C and assembly firmware experience, are required.

  JTAG, Palladium, Veloce, Logic analyzer, Oscilloscope, Python

  23d

  RTL Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a Bachelor's or Master's degree in electrical or computer engineering, computer science or a related field, with Verilog and SystemVerilog skills, scripting experience, and knowledge of bus protocols such as AXI and AHB. Experience with ASIC design tools and CPU or microprocessor subsystem architecture is preferred.

  Verilog, Tcl, Ruby, Perl, Python, Makefile

  23d

  RTL/Firmware Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a Bachelor's or Master's in computer engineering, electrical engineering, computer science or a related field. Embedded C/C++, reading Verilog or SystemVerilog, Python scripting and analytical problem-solving are preferred.

  Verilog, SystemVerilog, Git, Perforce, Jenkins, Python

  23d

  Sr. Systems Validation Engineer – Data Center GPU

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a bachelor's or master's degree in an engineering or computer science field, plus strong experience in SoC or system validation, silicon bring-up and data center debug. Python and C/C++ skills, and familiarity with Linux and register-level debug, are preferred.

  Python, C/C++, Linux, FPGA

  23d

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

  23d

  Principal ASIC Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a track record of leading ASIC or silicon designs through multiple product tape-outs, plus deep RTL and microarchitecture experience. Strong communication skills and the ability to lead technical reviews are also required.

  Verilog, SystemVerilog, Python, Perl, Tcl

  23d

  Senior Firmware Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need extensive experience with microcontrollers and embedded C or assembly, strong low-level hardware and firmware interface knowledge, and a bachelor's or master's degree in electronics, computer engineering or another applied science.

  Git, GitHub Actions, Python, RTOS, emulation platforms, RTL simulation tools

• 17d

  Senior ASIC Design Engineer - DSP/Analog/SerDes

  Ottawa, ON

  CC

  Celero Communications, Inc.

  10+ YOECandidates need a master's or PhD in electrical or computer engineering, 10+ years of digital ASIC design, and strong Verilog or SystemVerilog skills. Knowledge of DSP, high-speed SerDes, mixed-signal or optical communications is also required.

  Verilog, SystemVerilog, Python, Tcl, MATLAB, UVM

• 17d

  Analog Design, Architect - 18618

  Mississauga, ON

  S

  Synopsys

  10+ YOECandidates need a PhD with 10+ years or MSc with 12+ years of SerDes or high-speed analog design experience. Synopsys expects silicon-proven TX, RX and clock circuit work, transistor-level CMOS and FinFET layout skills, and some leadership of small teams.

  SPICE, Verilog-A, TCL, Perl, C, Python

• 18d

  Senior Principal Embedded Software Architect

  Vancouver, BC

  Full Time

  C

  Canada

  15+ YOE3+ MgmtAnalog Devices Canada needs 15+ years of embedded system software and HW/SW co-design experience, plus a BS or MS in engineering or computer science. Candidates need 3+ years of engineering management, expert C/C++ for RTOS and Embedded Linux, and knowledge of ARM or RISC-V and bus protocols.

  JTAG, Zephyr, Embedded Linux, Verilog, SystemVerilog, CoreSight

• 19d

  ASIC Verification Intern - Summer 2027

  Toronto, ON

  Full Time

  NC

  NVIDIA Canada Dev. Inc.

  Candidates need to be pursuing a BS or MS in Electrical or Computer Engineering. They need working knowledge of computer architecture, logic design, verification, algorithms and data structures, plus strong first-principles debugging and teamwork skills.

  Verilog, SystemVerilog, UVM, FPGA, Linux, Windows

• 21d

  FPGA Developer / FPGA Design Engineer (4G/5G Radio – Datapath / RU FPGA Design)

  Ottawa, ON

  Contract

  

  Myticas Consulting

  1+ YOECandidates need strong FPGA and DSP fundamentals, SystemVerilog and MATLAB/Simulink experience, and knowledge of AXI and Ethernet. Radio protocol knowledge such as O-RAN, eCPRI and PTP is desirable, and 1 to 5 years of experience is encouraged.

  Altera Quartus, MATLAB, Simulink, SystemVerilog

• 22d

  GPU Design Verification Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need experience with IP-level ASIC verification, UVM testbenches, Verilog and SystemVerilog, and scripting in Python or Perl. Advanced Micro Devices prefers a Bachelor's or Master's in computer or electrical engineering.

  Verilog, UVM, C/C++, Perl, Python, Makefile

  23d

  Firmware Engineering Manager

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need engineering management experience building teams and deep GFX or SOC architecture and debug skills. They also need hands-on C and assembly firmware experience and a degree in electrical or computer engineering or computer science.

  JTAG, logic analyzer, oscilloscope, Palladium, Veloce, Python

• 22d

  Principal Engineer, CAD

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  7+ YOECandidates need a BA or BS in electrical engineering, computer science or a related field and at least 7 years of CMOS IC CAD support experience. They must know Cadence, Synopsys and Siemens EDA tools, scripting languages such as SKILL, Python and Tcl, and Linux.

  Cadence Virtuoso, Spectre, Assura, Innovus, Tempus, Synopsys Design Compiler

  22d

  ASIC Digital Verification Engineer

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  Candidates need knowledge of chip specifications and verification plans, plus SystemVerilog and UVM for digital verification. Experience with Synopsys or Cadence simulators, SystemVerilog assertions, functional and code coverage, and working in Unix/Linux is also needed.

  SystemVerilog, UVM, Unix, Linux

• 23d

  Senior ASIC Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  2+ YOECandidates need a Bachelor's in electrical engineering (a Master's is preferred) and 2+ years supporting complex SoC silicon for server, storage or networking. They must have hands-on UVM, C/C++ and System Verilog experience, plus experience with third-party protocol VIPs such as PCIe, Ethernet and DDR.

  System Verilog, UVM, Perl, Python

  23d

  Senior Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  3+ YOETalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.

  SystemVerilog, UVM, Python, Perl, C/C++, GNU Make

  23d

  Staff ASIC Design Engineer – AI/ML Hardware IP

  Toronto, ON

  T

  Talentlab

  5+ YOECandidates need at least 5 years of hands-on ASIC design experience and strong skills in Verilog, SystemVerilog, and logic synthesis. A degree in electrical or computer engineering is required, and candidates must be legally authorized to work on-site in Canada.

  Verilog, SystemVerilog, Design Compiler, PrimeTime, Formality, Spyglass

  23d

  Senior Staff ASIC Design Egineer - AI/ML Hardware IP

  Toronto, ON

  T

  Talentlab

  6+ YOECandidates need six or more years of ASIC design and integration experience (or a Master's plus five years, or a PhD plus four), strong Verilog/SystemVerilog skills, and experience owning complex SoC blocks. A Bachelor's, Master's or PhD in electrical engineering or a related field is required, and the candidate must be legally authorized to work in Canada.

  Verilog, SystemVerilog, VCS, Verdi, Questa, Xcelium

• 23d

  Digital Design Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer engineering, computer science or a related field. They need digital logic or RTL coursework or project experience, programming skills in Verilog, SystemVerilog, C/C++ or Python, and familiarity with Linux and Git.

  Verilog, SystemVerilog, Linux, Git, Python, Tcl

11 companies