FY27 Intern - Applied AI Engineering Intern (Hardware Systems) - Canada (16 months)
Vancouver, BCQualcomm Canada ULC
Candidates need to be pursuing a BS or MS in electrical, computer engineering, computer science or a related field, with strong Python and/or C/C++ skills. Digital design knowledge, Linux familiarity and a passion for AI and LLMs are required, and Verilog, SystemVerilog and FPGA experience is preferred.
Python, C/C++, SystemC, SystemVerilog, Linux, Git
FY27 Intern - Camera Design Implementation Intern - Canada (16 months)
Vancouver, BCQualcomm Canada ULC
Candidates need to be enrolled in a bachelor's degree in engineering, computer science or a related field, with an expected graduation of November 2028 or later. Strong scripting skills and knowledge of ASIC design flow are needed.
synthesis tools, static timing analysis tools, formal verification tools
Camera Design Engineer
Vancouver, BCQualcomm Canada ULC
3+ YOECandidates need a bachelor's, master's or PhD in a computer, electrical or related engineering field, with 4 to 2 years of hardware or related experience depending on degree. Verilog or VHDL RTL design, design verification and bus protocol experience are key.
Verilog, VHDL, TCL, Perl, Python
FY27 Intern - Camera Systems Internship - Canada (16 months)
Vancouver, BCQualcomm Canada ULC
Candidates need to be enrolled toward a bachelor's or master's in engineering, computer science or a related field, and be available for a 16-month internship. Experience with microcontrollers, RTOS or ARM architectures, plus Android debugging and version control, is preferred.
JTAG, ADB, Android development environments, Version-control systems
ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a Bachelor's degree in engineering, science or a related field and 2+ years of ASIC design or verification work, or a new-grad co-op, internship or PEY background. Preferred skills include SystemVerilog, UVM, Verilog or VHDL, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python
ASICS Design Verification Engineer (Vancouver, Markham OR Remote)
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in engineering or science and 2+ years of ASIC design or verification experience. Preferred skills include SystemVerilog and UVM testbench development, RTL design, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python