“RTL Architect” jobs in Canada – Page 3

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• 1mo

  Sr. Manager - RTL Design Manager

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a proven record of engineering leadership and IP or RTL team management. They need strong Verilog/SystemVerilog skills, knowledge of ASIC design flows and a Bachelor's degree in engineering or computer science.

  Verilog, SystemVerilog, AMBA, AXI, AHB

  1mo

  Diagnostics Software/Hardware Technical Lead

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need industry experience in silicon engineering, such as post-silicon validation or test generation, plus strong C/C++ and Python skills. A Bachelor's, Master's or PhD in an engineering or computer science field is required.

  STIL, WGL, GitHub, CI/CD pipelines

  1mo

  RTL/Firmware Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in computer engineering, electrical engineering, computer science or a related field. Preferred skills include embedded C/C++, Verilog or SystemVerilog, Python scripting, computer architecture and hands-on use of AI coding tools.

  Verilog, SystemVerilog, Python, Perl, Git, Perforce

  1mo

  STA/Constraints Engineer

  Vancouver, BC

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need industry experience in static timing analysis, constraints and timing signoff, plus expert use of Synopsys PrimeTime and GCA. Scripting in Perl, TCL, Shell or Python, and a degree in microelectronics or a related field, are preferred.

  GCA, ICC2, Verilog, Perl, TCL, Python

• 1mo

  Senior I/O Chiplet Verification Engineer

  Ottawa, ON

  Full Time

  

  BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.

  10+ YOECandidates need 10 or more years of hands-on ASIC verification experience through tape-out sign-off, strong SystemVerilog and UVM skills, and experience with high-speed interfaces or die-to-die interconnect. Scripting, regression automation and clear written communication are essential.

  SystemVerilog, UVM, UPF

  1mo

  Senior I/O Chiplet RTL Design Engineer

  Ottawa, ON

  Full Time

  

  BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.

  10+ YOECandidates need 10+ years of hands-on ASIC RTL design with tape-out ownership, strong SystemVerilog and Verilog skills, and experience with high-speed interfaces such as PCIe, Ethernet or die-to-die links. They also need synthesis, timing constraint and CDC/RDC expertise, plus scripting in Python or Tcl.

  SystemVerilog, Verilog, Python, Tcl

• 1mo

  IC Design Engineer (BC/ ON)

  Burnaby, BC

  On-siteFull Time

  

  NETINT Technologies Inc.: NETINT Technologies develops custom silicon for ultra-high-density video encoding and processing in the data center.

  3+ YOECandidates need an MS or BS in Electrical or Computer Engineering and 3 to 5 years of IC or FPGA design experience. Strong Verilog and SystemVerilog coding, hardware debugging and verification skills are required.

  Verilog, Xilinx Vivado, FPGA

• 1mo

  Senior SoC Design Engineer

  Burnaby, BC

  $86k–$186k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  3+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering and 3 to 5 years of related experience, including RTL design in SystemVerilog and Verilog. Experience with ASIC design flows, synthesis, static timing analysis and PCI-Express is valued.

  Synopsys Design Compiler, Cadence Incisive, Verilog, Perl, Python, Tcl

• 1mo

  Senior ASIC Design Engineer - Client IP

  Ottawa, ON

  $112k–$179k/yrFull Time

  CC

  Ciena Canada ULC

  5+ YOECandidates need an engineering degree at the bachelor or master level and 5+ years of SystemVerilog design and digital synthesis, timing closure and clock-crossing experience. Strong independent problem solving, English communication, and knowledge of verification and timing/power/area trade-offs are required.

  Git, Jira, Python, Make, bash

• 1mo

  Field Application Engineer - AMD/Xilinx

  Pointe-Claire, QC

  Full Time

  AC

  Avnet Canada

  8+ YOECandidates need systems-level experience with FPGA and ASIC design tools, especially Vivado/Vitis, ISE or Quartus. They also need strong communication and problem-solving skills and typically 8+ years of experience with a bachelor's degree or equivalent.

  Vivado, Vitis, ISE, Quartus, ModelSim, IP Integrator

• 1mo

  Confidential Computing Software Architect

  Canada

  Full Time

  

  SiFive, Inc.

  Candidates need prior experience implementing system software for confidential compute workloads, familiarity with Intel, AMD and ARM confidential computing and trusted execution environments, strong software engineering skills in C, and experience writing and reviewing specifications.

  C, Linux, RISC-V

  1mo

  Linux Kernel Architect

  Canada

  Full Time

  

  SiFive, Inc.

  Candidates need experience with concurrency-sensitive upstream Linux kernel code, debugging hardware and software bugs in CPUs and SoCs, and working with CPU architects. They also need experience with Linux on FPGA or emulation, hypervisors, and familiarity with the RISC-V architecture.

  Linux kernel, OpenSBI, hardware debuggers, FPGA, emulation platforms

• 1mo

  Power Architect

  Toronto, ON

  

  Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.

  15+ YOECandidates need 15+ years of experience with power estimation tools, deep knowledge of power-gating, voltage domains and leakage control, and a record of reducing design power through architectural changes. Proficiency in Verilog, Design Compiler, C/C++ and Python is required.

  PowerArtist, PtPX, RTL Architect, PrimePower, Verilog HDL, Design Compiler

• 1mo

  Lead SOC Architect

  Canada

  HybridFull Time

  

  NUVACORE

  20+ YOECandidates need 20+ years of SoC or system architecture experience from definition through production. Deep knowledge of coherent interconnects, cache hierarchies, DDR/LPDDR memory controllers, PCIe/CXL and die-to-die links is required, along with an MS or PhD or equivalent experience.

  Scheduling, Translation, Packaging, RTL, Firmware, Communication skills

  1mo

  CPU Verification Engineer

  Markham, ON

  HybridFull Time

  

  NUVACORE

  4+ YOECandidates need a degree in electrical or computer engineering or computer science (or equivalent experience), 4+ years (Senior) or 15+ years (Principal) of design verification, CPU microarchitecture knowledge, and skill in C/C++ or SystemVerilog plus Python.

  SystemVerilog, C/C++, Python, Perl, FPGA

  1mo

  CPU Architecture Verification Engineer

  Markham, ON

  HybridFull Time

  

  NUVACORE

  4+ YOECandidates need a degree in electrical or computer engineering, computer science or equivalent experience, plus 4+ years (Senior) or 15+ years (Principal) of design verification. They need strong CPU architecture knowledge, one modern ISA (x86, ARM or RISC-V), and skill in C/C++/Rust or SystemVerilog with Python.

  SystemVerilog, Python, Perl, FPGA

• 1mo

  Senior FPGA Designer

  Montréal, QC

  HybridFull Time

  E

  Exegy

  5+ YOEDiplôme en génie électronique, électrique ou informatique; Cinq ans ou plus d'expérience en conception FPGA; Maîtrise avancée du VHDL et/ou du Verilog

  Vivado, Git, Jenkins, Python, Linux

• 1mo

  Sr. Staff ASIC Design Methodology Engineer, AI HW

  Toronto, ON

  

  Tenstorrent Unlisted/Referral Jobs: Tenstorrent is a next-generation computing company that builds computers for AI.

  Candidates need deep ASIC design flow expertise, strong RTL design skills and experience with static and dynamic analysis tools for high-performance hardware. Senior-level experience leading methodology improvements and collaborating across teams is expected.

  Lint, CDC tools, RDC tools, DFT tools, SDC, UPF

• 1mo

  Principal Digital Architect

  Toronto, ON

  

  Lightmatter

  12+ YOECandidates need 12+ years of experience and a Master's degree in Electrical or Computer Engineering, with hands-on RTL and control logic work and proven high-volume silicon delivery. Strong problem solving across digital, analog, photonic and firmware domains and clear customer communication are required.

  SPICE, IBIS-AMI, MATLAB, Python, CAD tools, FPGA

  1mo

  Digital Architect

  Toronto, ON

  

  Lightmatter

  3+ YOECandidates need 3+ years of experience and a Master's degree in Electrical or Computer Engineering, plus knowledge of power-efficient digital design for high-speed analog or photonic links. Strong problem solving, written and verbal communication, and tool skills in SPICE, IBIS-AMI, MATLAB or Python are expected.

  SPICE simulators, IBIS-AMI simulators, MATLAB, Python, CAD tools

• 1mo

  Senior ASIC (Front End) Design Engineer

  Toronto, ON

  Hybrid

  

  Ethernovia, Inc.

  10+ YOECandidates need a BS or MS in electrical engineering, computer science or a related field and 10+ years of ASIC RTL design or architecture experience. They must have built complex SoCs, know Verilog/SystemVerilog and simulation tools, and work well both independently and in teams.

  Verilog, Perl, TCL, C/C++, Make

13 companies