DDR Validation Lead, Staff (AI Accelerator Platform)
Markham, ONQualcomm Technologies, Inc.
5+ YOECandidates need at least 5 years in DDR or memory subsystem validation or silicon bring-up, plus knowledge of LPDDR architectures, memory controllers and PHYs, and strong post-silicon debug skills. Qualcomm also requires a bachelor's, master's or PhD and C/C++ proficiency.
emulation platforms, FPGA, C, C++
SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)
Markham, ONQualcomm Technologies, Inc.
7+ YOEQualcomm needs a candidate with 7+ years of silicon validation or platform bring-up experience and deep knowledge of NoCs, AXI, memory hierarchy, power modes and debug. A degree in engineering or computer science is required, with embedded C/C++, Python and assembly skills.
JTAG debugger, Perfmon, kernel debugger, emulation platform
System Validation Lead (Premium Mobile Platforms)
Markham, ONQualcomm Technologies, Inc.
8+ YOECandidates need 8+ years of SoC validation, bring-up, or system software experience, deep knowledge of modern SoC architectures such as ARM CPUs, memory and interconnects, and proven pre- and post-silicon validation and debug skills. Leadership of geographically distributed teams is required.
Veloce, RUMI, FPGA
System Validation Lead, Staff (AI Accelerator Platform)
Markham, ONQualcomm Technologies, Inc.
8+ YOECandidates need 8+ years of silicon validation or platform bring-up experience, strong C and Assembly skills, and bare-metal embedded knowledge. A BS, MS or PhD in an engineering or computer science field is required, plus the minimum years of ASIC work listed for each degree.
FPGA, Verilog, VHDL, Python, Linux shell, development boards
SoC Debug Engineer, Senior Staff
Markham, ONQualcomm Technologies, Inc.
9+ YOECandidates need 9+ years of pre-silicon and post-silicon bring-up and debug experience, RTL understanding, and hands-on use of JTAG and lab equipment such as logic analyzers and oscilloscopes. A Master's in Computer or Electrical Engineering is required, along with the stated years of ASIC design or validation experience.
JTAG, Logic analyzer, Signal generator
SoC Debug Engineer, Staff
Markham, ONQualcomm Technologies, Inc.
6+ YOECandidates need 6+ years of pre-silicon and post-silicon bring-up and failure analysis experience, plus RTL understanding and JTAG and lab equipment skills. A Master's in Computer or Electrical Engineering is required, along with ASIC experience.
JTAG, Logic analyzer, Signal generator