Lead Digital Verification Engineer
Mount Royal, SKFull Time
C
Cadence
Candidates need an engineering degree in electrical, computer or computer science, plus understanding of verification methodologies such as UVM and metric-driven verification. Strong problem-solving skills, English communication and experience with SystemVerilog assertions are required.
SystemVerilog, UVM, Python, Perl, Ruby, Cadence tools
Lead Digital Verification Engineer
Mount Royal, SKFull Time
C
Cadence
Candidates need an engineering degree in electrical, computer or computer science, plus understanding of verification methodologies such as UVM and metric-driven verification. Strong problem-solving skills, English communication and experience with SystemVerilog assertions are required.
SystemVerilog, UVM, Python, Perl, Ruby, Cadence tools