RTL/Firmware Design Engineer
Markham, ONAMD, Inc.
Candidates need a Bachelor's or Master's in computer engineering, electrical engineering, computer science or a related field. Embedded C/C++, reading Verilog or SystemVerilog, Python scripting and analytical problem-solving are preferred.
Verilog, SystemVerilog, Git, Perforce, Jenkins, Python
Silicon Design Engineer
Markham, ONAMD, Inc.
Candidates need a bachelor's degree in electrical or computer engineering, with a master's or PhD preferred. AMD wants hands-on ASIC firmware and hardware verification experience with UVM, SystemVerilog, C/C++ and bus protocols such as AXI and AHB.
UVM, Verilog, C-DPI, Python, Perl, Make
CPU Performance Engineer
Markham, ONAMD, Inc.
Candidates need a degree in computer engineering or computer science, with computer architecture experience preferred. Strong analytical skills, C/C++ programming, and knowledge of CPU, GPU or DRAM microarchitecture are preferred.
C, C++
Silicon Design Engineer - Technical Lead
Markham, ONAMD, Inc.
AMD needs candidates with experience in I/O protocols such as USB, PCIe and CXL, plus micro-architecture and RTL design for multi-clock, high-frequency, low-power designs. A master's or bachelor's in electrical engineering or equivalent is preferred.
Python, Perl
Silicon Design Verification Engineer
Markham, ONAMD, Inc.
Candidates need a Bachelor's or Master's in Computer or Electrical Engineering, knowledge of digital design and computer architecture, and hands-on SystemVerilog, UVM and C++ or Python experience. Prior verification work and PCIe or AXI protocol knowledge are assets.
UVM, C++, Python, Formal verification tools
RTL Design Engineer
Markham, ONAMD, Inc.
Candidates need experience with I/O protocols such as USB, PCIe and CXL, plus RTL design for multi-clock, high-frequency, low-power designs. A bachelor's or master's degree in electrical engineering or equivalent is preferred.
Python, Perl
Physical Design Engineer
Markham, ONAMD, Inc.
Candidates need hands-on ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and tape-out experience on advanced nodes such as 3nm, 5nm, 7nm or 16nm. A bachelor's or master's degree in computer or electrical engineering is required.
Synopsys, Cadence, Mentor Graphics, Verilog
Senior ASIC RTL Design Engineer, AI Networking IP
Ottawa, ONAMD, Inc.
Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.
Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python
Sr. Manager - RTL Design Manager
Markham, ONAMD, Inc.
AMD needs a leader with experience managing IP or RTL design teams and strong Verilog/SystemVerilog skills. Candidates should know RTL microarchitecture, ASIC verification flows and on-chip protocols such as AXI and AHB, and hold a bachelor's degree in an engineering or computer discipline.
Verilog, SystemVerilog
Principal ASIC Design Engineer
Markham, ONAMD, Inc.
Candidates need a track record of leading ASIC or silicon designs through multiple product tape-outs, plus deep RTL and microarchitecture experience. Strong communication skills and the ability to lead technical reviews are also required.
Verilog, SystemVerilog, Python, Perl, Tcl
Senior Firmware Engineer
Markham, ONAMD, Inc.
Candidates need extensive experience with microcontrollers and embedded C or assembly, strong low-level hardware and firmware interface knowledge, and a bachelor's or master's degree in electronics, computer engineering or another applied science.
Git, GitHub Actions, Python, RTOS, emulation platforms, RTL simulation tools
Design Verification Lead
Markham, ONAMD, Inc.
Candidates need a bachelor's or master's degree in electrical or computer engineering, computer science or a related field, plus UVM and SystemVerilog experience and knowledge of high-speed protocols such as PCIe, CXL or Ethernet. Scripting in Python or Perl and technical leadership skills are also needed.
SystemVerilog, Verilog, UVM, Python, Perl