Staff Physical Design Engineer
Toronto, ONTalentlab
5+ YOECandidates need 5+ years of physical design experience on digital ASICs, including advanced nodes like TSMC N5, N4P or N3. They must know industry EDA tools, PnR, timing analysis and physical verification, and be strong in TCL, Python or Perl.
Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk, TCL
Staff ASIC Design Engineer – AI/ML Hardware IP
Toronto, ONTalentlab
5+ YOECandidates need at least 5 years of hands-on ASIC design experience and strong skills in Verilog, SystemVerilog, and logic synthesis. A degree in electrical or computer engineering is required, and candidates must be legally authorized to work on-site in Canada.
Verilog, SystemVerilog, Design Compiler, PrimeTime, Formality, Spyglass
Senior Staff ASIC Design Egineer - AI/ML Hardware IP
Toronto, ONTalentlab
6+ YOECandidates need six or more years of ASIC design and integration experience (or a Master's plus five years, or a PhD plus four), strong Verilog/SystemVerilog skills, and experience owning complex SoC blocks. A Bachelor's, Master's or PhD in electrical engineering or a related field is required, and the candidate must be legally authorized to work in Canada.
Verilog, SystemVerilog, VCS, Verdi, Questa, Xcelium