“Synopsys tools” jobs in Canada – Page 6

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• 1mo

  Senior SoC Design Engineer

  Burnaby, BC

  $86k–$186k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  3+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering and 3 to 5 years of related experience, including RTL design in SystemVerilog and Verilog. Experience with ASIC design flows, synthesis, static timing analysis and PCI-Express is valued.

  Synopsys Design Compiler, Cadence Incisive, Verilog, Perl, Python, Tcl

  1mo

  Senior Manager-Design Engineering

  Burnaby, BC +2

  Full Time

  MS

  MCHP Semiconductor Canada ULC

  12+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering, 12+ years of related experience and proven experience leading engineering teams. Strong coaching skills, debugging ability and Verilog or VHDL design experience are required; SOC, communication protocols, Synopsys or Cadence tools and 28nm process experience are assets.

  Verilog, VHDL, Synopsys, Cadence

• 1mo

  Mixed Signal Design Engineer

  Ottawa, ON

  $93k–$149k/yrFull Time

  CC

  Ciena Canada ULC

  Ciena Canada ULC needs a degree in electrical or computer engineering, computer science or a related science. Candidates need CMOS or BiCMOS design experience and skill with Cadence, Synopsys and Siemens EDA tools, plus SystemVerilog, Verilog-AMS, Python and C/C++.

  Cadence Virtuoso, Cadence Xcelium, Cadence AMS, Synopsys VCS, Synopsys StarRC, Siemens Questa

• 1mo

  Lead DFT Engineer

  Remote in Canada

  Remote

  

  EnCharge AI

  12+ YOE2+ MgmtCandidates need 12+ years of DFT experience, including at least 2 years in a lead or principal role, and a bachelor's degree in a related field. Deep expertise in memory and logic test, FinFET advanced nodes, and low-power DFT is required.

  Synopsys TestMAX, Siemens Tessent, Cadence Modus, ATE (Automated Test Equipment)

• 1mo

  Digital - Staff Digital Design Engineer - PHY

  Canada

  On-siteFull Time

  E

  Eliyan

  8+ YOEEliyan needs 8+ years of digital frontend design with 4+ years in PHY or high-speed interfaces, and 3+ tapeouts as design lead at 7nm or below. Candidates need expert SystemVerilog, synthesis, CDC and UCIe or DDR/SerDes knowledge.

  SystemVerilog, Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, UPF, SDC

• 1mo

  Formal Verification Engineer

  Markham, ON

  HybridFull Time

  

  NUVACORE

  4+ YOECandidates need a degree in electrical or computer engineering, computer science or mathematics, or equivalent experience. They must have hands-on formal verification experience, strong SystemVerilog and assertion skills, CPU microarchitecture knowledge and Python scripting.

  SystemVerilog, Verilog, Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, Python

• 1mo

  Senior Digital Design Engineer

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  2+ YOECandidates need a bachelor's degree in electrical or electronics engineering, 2 to 5 years of digital design experience on complex chips, and hands-on SystemVerilog or Verilog RTL skills. PCIe or Ethernet IP experience and Python or Perl scripting are also required, and candidates must be authorized to work in Canada.

  SystemVerilog, Verilog, Synopsys, Cadence, Python, Perl

• 1mo

  Staff Photonics Design & PDK Modeling Engineer

  Toronto, ON

  

  Lightmatter

  5+ YOELightmatter needs a Master's with 5+ years or a PhD with 3+ years in electrical engineering, photonics, physics or a related field. Candidates need photonic device physics, behavioral modeling for circuit simulators, and strong Python with NumPy and SciPy.

  Python, KLayout, GDSFactory, gdstk, Lumerical INTERCONNECT, Cadence Virtuoso

  1mo

  Sr. Staff Physical Design Timing Engineer (STA)

  Toronto, ON

  

  Lightmatter

  12+ YOELightmatter needs candidates with a bachelor's degree in electrical or computer engineering and 12 years of physical design experience, including 5 years of hands-on ASIC timing work. They must be skilled in Cadence or Synopsys timing tools and scripting in TCL and Python, Perl, or Shell.

  Synopsys PrimeTime, Cadence Tempus

7 companies