“System Verilog” jobs in Canada – Page 6

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• 1mo

  Analog Design, Manager - 18463

  Kanata, ON

  S

  Synopsys

  8+ YOE2+ MgmtCandidates need an M.A.Sc. with 8+ years or a PhD with 6+ years of analog or mixed-signal IC design experience, plus 2+ years of people management. They must have deep Multi-Gbps SerDes expertise, transistor-level design skills, and experience with SPICE, Verilog-A and layout.

  SPICE, Verilog-A, Industry-standard simulation tools

  1mo

  Senior Staff Hardware Validation Engineer

  Mississauga, ON

  S

  Synopsys

  6+ YOESynopsys needs a bachelor's degree in electrical or electronic engineering with 8 years of relevant experience, or a master's with 6 years. Candidates need lab test equipment experience, PCB fabrication house experience and skill running PI and SI simulations.

  HFSS, high-speed scopes, power meters, IR cameras, FPGA development tools, Verilog HDL

  1mo

  ASIC Digital Verification, Sr. Manager

  Mississauga, ON

  S

  Synopsys

  15+ YOECandidates need a BS or MS in EE, EC or VLSI with 15+ years of IP or SoC verification experience, and strong team leadership. They must know Verilog, SystemVerilog and UVM, and Perl or Python automation. PCIe and Ethernet knowledge is an asset.

  Verilog, SystemVerilog, UVM, Perl, Python

• 1mo

  Avionics Certification Engineer – DO-178C, DO-254, FPGA/ASIC & Embedded Systems

  Montréal, QC

  AN

  Astra North Infoteck Inc.

  15+ YOEAstra North Infoteck Inc. needs candidates with deep experience in aircraft software and hardware certification, including DO-178C and DO-254. They also need FPGA or ASIC design experience, requirements tools like DOORS or JAMA, and experience with FAA and EASA rules.

  DOORS, JAMA

• 1mo

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's in computer or electrical engineering, and strong Verilog or SystemVerilog RTL design skills. Experience delivering ASIC or FPGA products, plus networking or high-speed interface knowledge, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

  1mo

  3D IC and ADVANCED PACKAGING CAD ENGINEER

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in computer or electrical engineering, experience with 3D-IC design and advanced packaging, and hands-on work with Synopsys 3DIC Compiler. Strong scripting skills and experience applying AI to CAD or hardware design are also needed.

  Synopsys 3DIC Compiler, Synopsys EDA tools, Cadence EDA tools, Linux/Unix, Python, TCL

  1mo

  Physical Design Engineer

  Vancouver, BC

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in computer or electrical engineering and hands-on ASIC physical design experience from RTL to GDSII. Strong Verilog, timing analysis, low-voltage design and advanced-node tape-out experience (3nm to 16nm) are preferred.

  Synopsys tools, Cadence tools, Mentor Graphics tools, Verilog

  1mo

  Design Verification Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need hands-on hardware verification experience across multiple projects or tapeouts, with SystemVerilog, UVM, Verilog and scripting skills. A Bachelor's or Master's in Computer or Electrical Engineering is expected.

  UVM, Verilog, Makefiles, Perl, Python, Ruby

  1mo

  Verification Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need strong SystemVerilog and UVM skills, solid ASIC/SoC verification experience, and familiarity with constrained-random, coverage-driven and formal (SVA) methods. A bachelor's or master's in computer or electrical engineering is required.

  Synopsys VCS, Cadence IES, Cadence IEV, Jasper, VC-Formal, Magellan

  1mo

  Silicon Design Verification Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's in Computer or Electrical Engineering, plus knowledge of digital logic and computer architecture. Experience with SystemVerilog, UVM, C++ and Python, and protocols such as PCIe or AXI, is preferred.

  UVM, C++, Python, SVA formal tools

  1mo

  Physical Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates at Advanced Micro Devices need ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and hands-on tape-out experience on 3nm to 16nm SoCs. They also need experience with Synopsys, Cadence or Mentor Graphics CAD tools and a bachelor's or master's degree in electrical or computer engineering.

  Synopsys tools, Cadence tools, Mentor Graphics tools, Verilog

  1mo

  Firmware Engineer

  Vancouver, BC

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's, Master's or PhD in Electrical or Computer Engineering, strong C, C++ and scripting skills, and firmware experience on pre- and post-silicon platforms. Experience with DDR/JEDEC IP, memory controllers or PHYs, and computer architecture is needed.

  oscilloscope, logic analyzer, VCS, FPGA

  1mo

  RTL/Firmware Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in computer engineering, electrical engineering, computer science or a related field. Preferred skills include embedded C/C++, Verilog or SystemVerilog, Python scripting, computer architecture and hands-on use of AI coding tools.

  Verilog, SystemVerilog, Python, Perl, Git, Perforce

  1mo

  Silicon Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's degree in electrical or computer engineering, with a master's or PhD preferred. Experience with ASIC hardware and firmware design and verification, C/C++ and SystemVerilog, and bus protocols like AXI and AHB is preferred.

  UVM, C-DPI, Verilog, FPGA prototyping platforms, Python, Perl

  1mo

  SoC Lead Engineer – LEC & Low Power Signoff

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Advanced Micro Devices needs candidates with proven SoC implementation and tapeout experience, deep knowledge of equivalence checking and low power verification, and hands-on use of industry EDA tools. Strong scripting, debugging, leadership and communication skills are also required, along with a BS or MS in Electrical Engineering, ECE, EEE or a related field.

  Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler

  1mo

  STA/Constraints Engineer

  Vancouver, BC

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need industry experience in static timing analysis, constraints and timing signoff, plus expert use of Synopsys PrimeTime and GCA. Scripting in Perl, TCL, Shell or Python, and a degree in microelectronics or a related field, are preferred.

  GCA, ICC2, Verilog, Perl, TCL, Python

• 1mo

  Firmware Engineer, Staff

  Toronto, ON

  On-site

  

  Qualcomm Canada ULC

  6+ YOECandidates need a bachelor's, master's or PhD in a related field plus 4, 3 or 2 years of software engineering experience respectively, and 6+ years with embedded systems and strong C/C++ and Python skills. Hands-on lab bring-up and debugging experience with high-speed signals and protocols such as PCIe and Ethernet is expected.

  oscilloscope, JTAG debugger, EDA tools, Jira, Confluence

  1mo

  Digital Design Verification Engineer, Staff

  Toronto, ON

  On-site

  

  Qualcomm Canada ULC

  4+ YOECandidates need a bachelor's degree in a science or engineering field with 4+ years of ASIC design or verification experience, or an equivalent master's or PhD with less experience. Strong SystemVerilog, UVM and scripting skills and proven leadership and communication are required.

  Verilog, SystemVerilog, UVM, Python, Perl, C/C++

  1mo

  Firmware Engineer – SerDes PHY (all levels)

  Toronto, ON

  On-site

  

  Qualcomm Canada ULC

  6+ YOECandidates need an engineering or computer science degree and 4 to 6+ years of software engineering experience, depending on degree level. They also need at least 3 years of programming experience in languages such as C, C++, Java or Python.

  JTAG debuggers, git, Verilog, SystemVerilog

  1mo

  Design Verification Engineer — Memory Subsystem (Vancouver)

  Vancouver, BC

  On-site

  

  Qualcomm Canada ULC

  3+ YOECandidates need a bachelor's or master's degree in an engineering or computer science field and 3 to 10 years of chip or subsystem verification experience. Hands-on skill with Verilog, SystemVerilog, UVM and assertions is required, and knowledge of memory standards such as DDR, LPDDR and HBM is preferred.

  Verilog, SystemVerilog, UVM, SystemVerilog Assertions, waveform viewers

• 1mo

  ASIC Verification Engineer (7745)

  Ottawa, ON

  T

  TSMC

  5+ YOECandidates need a master's or PhD in electrical or computer engineering and 5-10 years of digital verification experience. They should be strong in SystemVerilog, UVM, assertions, Unix/Linux and EDA tools such as VCS or Incisive.

  Synopsys VCS, Cadence Incisive, UVM, Unix/Linux

• 1mo

  FPGA Designer Coop (Waterdown, CAN)

  Waterdown, ON

  $25/hr

  

  L3Harris Technologies

  Candidates need to be enrolled in an accredited university co-op program in good standing, and able to obtain CGP clearance. They need basic VHDL, an understanding of timing closure, revision control experience, and strong English writing skills.

  Xilinx design tools, Questa Sim, VHDL, Git, SVN

• 1mo

  Senior I/O Chiplet RTL Design Engineer

  Ottawa, ON

  Full Time

  

  BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.

  10+ YOECandidates need 10+ years of hands-on ASIC RTL design with tape-out ownership, strong SystemVerilog and Verilog skills, and experience with high-speed interfaces such as PCIe, Ethernet or die-to-die links. They also need synthesis, timing constraint and CDC/RDC expertise, plus scripting in Python or Tcl.

  SystemVerilog, Verilog, Python, Tcl

• 1mo

  Senior Hardware Engineer

  Burnaby, BC

  $108k–$153k/yrFull Time

  

  LMI Technologies

  5+ YOECandidates need a bachelor's degree in electrical engineering and at least five years designing and testing digital logic such as FPGAs or ASICs. Hands-on experience with VHDL or Verilog, high-speed interfaces and self-verifying simulation environments is required.

  Vivado, Chipscope, Logic analyzers, Oscilloscopes, Xilinx IP, Intel FPGA

8 companies