“PCIe IP” jobs in Canada

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• 20d

  ASIC Design Engineer, PCIe IP Enablement

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need hands-on ASIC hardware design experience with end-to-end ownership of complex digital IP through tape-out. Strong RTL and Verilog skills, low-power design knowledge and a Bachelor's or Master's in electrical or computer engineering are preferred.

  Verilog HDL, UPF, CPF, Lint tools, CDC tools, Synthesis tools

• 20d

  ASIC Design Engineer, PCIe IP Enablement

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need hands-on ASIC hardware design experience with end-to-end ownership of complex digital IP through tape-out. Strong RTL and Verilog skills, synthesis and CDC tool experience, and knowledge of low-power design are expected.

  Verilog, UPF, CPF

• 25m

  Staff PCIe Verification Engineer

  Toronto, ON

  A

  ARM

  7+ YOEArm needs candidates with a Bachelor's or Master's degree in computer science or electrical or computer engineering and 7+ years of PCIe or CXL verification experience. They must have strong Verilog and UVM skills, simulation and emulation experience, and knowledge of formal methods.

  SystemVerilog, Verilog, UVM, PCIe IP, CXL IP, Emulation platforms

  25m

  Senior PCIe Design Engineer

  Toronto, ON

  A

  ARM

  5+ YOEArm needs candidates with a Bachelor's or Master's degree in a related engineering or computer science field and 5+ years of SoC or compute subsystem design experience. Candidates need Verilog, PCIe, CXL or Ethernet integration experience and scripting skills in Perl or Python.

  Verilog HDL, Perl, Python

  25m

  Senior PCIe Verification Engineer

  Toronto, ON

  A

  ARM

  4+ YOECandidates need a Bachelor's or Master's degree in a related engineering or computer science field and 4+ years of PCIe or CXL verification experience. Strong skills in Verilog, UVM, debugging and simulation or emulation platforms are required.

  SystemVerilog, Verilog, UVM, Debuggers, Simulation platforms, Emulation platforms

  25m

  Staff PCIe Design Engineer

  Toronto, ON

  A

  ARM

  10+ YOECandidates need a Bachelor's or Master's degree in computer science or electrical or computer engineering, 10+ years designing complex SoCs or compute subsystems, and strong Verilog and digital design skills. Experience with PCIe, CXL, UCIe or Ethernet subsystems and static design checks is required.

  Verilog HDL, Perl, Python

• 16h

  FPGA Design Engineer

  Ottawa, ON

  $65–$85/hrContract

  

  Actalent: Actalent is an operating company of Allegis Group, the global leader in talent solutions.

  5+ YOECandidates need 5+ years of ASIC/FPGA design experience, strong SystemVerilog skills, hands-on Cadence simulation experience, and practical debug and timing analysis skills. VHDL, Xilinx Vivado, Python, C/C++, DSP and high-speed interface experience are assets.

  SystemVerilog, Xilinx, Vivado, Cadence simulation tools, Python, C

• 16h

  AMS Design Verification Engineer

  Mississauga, ON

  S

  Synopsys

  5+ YOESynopsys needs candidates with a degree in electrical or computer engineering and strong knowledge of analog and mixed-signal circuits. Candidates should know SystemVerilog and UVM, have used AMS simulation tools, and be comfortable scripting in Python, Perl or shell.

  HSPICE, XA, CustomSim, VCS, SystemVerilog, UVM

  4d

  Principal Analog Mixed Signal Designer - 19497

  Mississauga, ON

  S

  Synopsys

  5+ YOECandidates need a PhD with 5+ years or a Master's with 8+ years of hands-on analog IC design experience. Strong CMOS skills, detailed SerDes sub-circuit design experience and SPICE simulation expertise are required.

  SPICE simulators, Verilog-A, schematic entry tools, physical layout tools, MATLAB, Python

  11d

  Sr Manager or Principal Engineer for Firmware Development - 19315

  Markham, ON

  S

  Synopsys

  10+ YOECandidates need a Bachelor's, Master's or PhD in computer or electrical engineering, or equivalent experience, with 10+ years in a related field. They need strong skills in digital logic and firmware development, proficiency in C, Verilog and SystemVerilog/UVM, and experience leading complex projects.

  Verilog, UVM, C, Python, Perl, Bash

  12d

  ASIC Digital Design, Sr Staff Engineer-19314

  Markham, ON

  S

  Synopsys

  8+ YOECandidates need a BS or MS in electronics or electrical engineering with 8+ years of digital verification experience in VMM or UVM. Strong Verilog and SystemVerilog testbench skills, debugging ability, and familiarity with Python or Perl are required.

  Verilog, SystemVerilog, UVM, VMM, Jira, Confluence

• 20h

  FPGA Design Verification Intern

  Toronto, ON

  Full Time

  AS

  Altera Semiconductor Technology Canada ULC

  Candidates need to be pursuing a bachelor's degree in computer engineering, engineering science, computer science, math, electrical engineering or equivalent, with at least 3 months of digital hardware design or verification experience and 3 months of software or scripting experience. Familiarity with FPGA tools such as Quartus and strong problem-solving skills are preferred.

  Quartus, Verilog, VHDL, C++, Python

• 4d

  Sr/Staff Digital Design Engineer

  Toronto, ON

  

  Lightmatter

  5+ YOELightmatter needs candidates with a bachelor's degree in electrical or computer engineering and at least 5 years of ASIC or high-speed chip design experience, including multiple successful tape-outs. Candidates must know SystemVerilog or Verilog and have proven experience debugging logic and mixed-signal simulations.

  SystemVerilog, Verilog, Synopsys VCS, Cadence Xcelium, Questa

• 6d

  Senior FPGA Research Engineer

  Vancouver, BC

  

  Barco

  7+ YOEBarco needs candidates with 7+ years of FPGA development, strong VHDL or Verilog/SystemVerilog skills, and experience with imaging sensor interfaces, high-speed transceivers and PCIe/DMA. Hands-on Quartus work, verification discipline and custom-board bring-up experience are required.

  Quartus, Agilex, Embedded logic analyzer, Oscilloscope, PCIe, DMA engines

• 7d

  Lead Digital Verification Engineer

  Montréal, QC

  Full Time

  C

  Cadence

  Candidates need a Bachelor's degree in electrical, computer engineering or computer science, plus knowledge of verification methodologies, metric driven verification, UVM, SystemVerilog assertions and the digital design flow. A Master's degree, UVM coding experience, scripting skills and protocol knowledge such as PCIe, USB or Ethernet are preferred.

  SystemVerilog, UVM, Python, Perl, Cadence tools

• 10d

  FY27 Intern - Soft IP ASIC Engineering Internship - Canada (12 or 16 months)

  Ottawa, ON

  On-siteInternship

  

  Qualcomm Canada ULC

  1+ YOEQualcomm Canada needs candidates studying toward a bachelor's degree in electrical, computer or engineering science, or computer science. They need scripting experience in Python, Perl, TCL or Unix/Linux shell, plus source control experience with SVN, CVS or RCS.

  Verilog, SystemVerilog, UVM, SVN, CVS, RCS

  10d

  DSP Systems Engineer, Staff

  Toronto, ON

  On-site

  

  Qualcomm Canada ULC

  4+ YOECandidates need a Bachelor's in engineering or a related field with 4+ years of systems engineering experience, or a Master's with 3+ years, or a PhD with 2+ years. Strong MATLAB, Python and C/C++ skills, plus DSP architecture experience in mixed-signal SerDes, are required.

  MATLAB, Python, C/C++, RTL simulation tools

  10d

  FY27 Intern - Softip Engineering Co-Op - Canada (4 months)

  Ottawa, ON

  On-siteInternship

  

  Qualcomm Canada ULC

  1+ YOECandidates need to be enrolled in a bachelor's or master's program in electrical, computer or related engineering, with scripting experience in Python, Perl, TCL or Unix/Linux shell and experience with source code revision systems.

  Verilog, SystemVerilog, UVM, VHDL, SVN, CVS

  10d

  FY27 Intern - Silicon Validation Internship - Canada (16 months)

  Toronto, ON

  On-siteInternship

  

  Qualcomm Canada ULC

  1+ YOEQualcomm Canada needs students in an engineering or computer science bachelor's program, available May/June 2027 to August/September 2028, with 1+ years of programming experience. Lab equipment experience and scripting in Python, Perl, TCL or Shell are preferred.

  oscilloscope, multimeter, Python, Perl, TCL, Shell

  10d

  Application Engineer, Sr Staff

  Toronto, ON

  On-site

  

  Qualcomm Canada ULC

  6+ YOECandidates need a bachelor's degree in electrical or computer engineering plus 6 or more years of hardware experience, or an equivalent advanced degree with fewer years. They need strong debugging skills, C/C++ for embedded systems, and Python for test automation.

  Oscilloscope, BERT, Protocol analyzer

  10d

  Verification Engineer (Engineer–Senior Level)

  Toronto, ON

  On-site

  

  Qualcomm Canada ULC

  2+ YOECandidates need a bachelor's degree in science or engineering with 2+ years of ASIC design or verification experience, or a master's with 1+ year, or a PhD. Strong SystemVerilog and UVM skills, constrained random verification experience and clear communication are required.

  SystemVerilog, UVM, Python, Perl, C/C++, GNU Make

  10d

  FY27 Intern - Firmware/Embedded Software Engineering Internship - Canada (12 or 16 months)

  Toronto, ON

  On-siteInternship

  

  Qualcomm Canada ULC

  1+ YOECandidates need to be enrolled in a bachelor's degree in electrical or computer engineering, engineering science or computer science, with at least one year of academic programming experience in C, C++ or Python. Strong debugging, problem-solving and teamwork skills are needed, and availability must match the 12- or 16-month internship dates.

  Git, Linux, FPGA, Verilog, SystemVerilog, GitHub Actions

• 18d

  Physical Design Engineering Director

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  15+ YOE5+ MgmtCandidates need a bachelor's degree in an electrical or computer engineering field, with 15+ years of physical design experience on advanced nodes and 5+ years leading teams. Hands-on skill with Cadence Innovus or Synopsys tools and scripting in Tcl, Python or Perl is required.

  Cadence Innovus, Synopsys Fusion Compiler, ICC2, Tcl, Python, Perl

• 18d

  FPGA Digital Design Engineer (6+ month Contract)

  Toronto, ON

  RemoteFull Time, Contract

  

  Kepler Communications

  5+ YOECandidates need a bachelor's degree in computer or electrical engineering, 5+ years of FPGA/RTL design experience, and skill in Verilog, SystemVerilog or VHDL. They also need Xilinx Zynq or UltraScale experience, timing and clock domain crossing knowledge, and scripting skills.

  Vivado, Quartus, ModelSim, Python, Tcl

12 companies