“SystemVerilog Assertions” jobs in Canada

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• 18h

  FY27 Intern - RF/Analog Verification Engineering Internship - Canada (4 or 16 months)

  Markham, ON

  On-siteInternship

  QC

  Qualcomm Canada ULC

  1+ YOECandidates need to be enrolled in a bachelor's, master's or PhD program in electrical, computer or computer science, with VLSI or RF/analog design coursework. Machine learning application experience and programming skills in Python or C++ are required.

  SystemVerilog, UVM, Python, C++, PyTorch, TensorFlow

  5d

  FY27 Intern - Design Verification Engineering Internship - Canada (16 months)

  Toronto, ON

  On-siteInternship

  QC

  Qualcomm Canada ULC

  1+ YOECandidates need to be enrolled in a bachelor's program in electrical, computer or engineering science, or a related field, with an expected graduation of November 2028 or later. They need at least one year of academic programming experience in C, C++ or Python, and are preferred with Verilog/SystemVerilog and verification methodology knowledge.

  Synopsys VCS, Verdi, SystemVerilog, Verilog, UVM

  6d

  Sr ASIC Design Verification Engineer, Low Power AI

  Markham, ON

  On-site

  QC

  Qualcomm Canada ULC

  2+ YOEQualcomm Canada ULC needs candidates with a bachelor's, master's or PhD and 2 to 4+ years of ASIC work, depending on degree. Expert skill in Verilog, SystemVerilog, UVM and C, plus a deep understanding of ASIC/VLSI concepts, is required.

  SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl

  7d

  ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham

  Vancouver, BC +1

  On-site

  QC

  Qualcomm Canada ULC

  2+ YOECandidates need a Bachelor's degree in engineering, science or a related field and 2+ years of ASIC design or verification work, or a new-grad co-op, internship or PEY background. Preferred skills include SystemVerilog, UVM, Verilog or VHDL, C or C++, and Python or Perl scripting.

  SystemVerilog, UVM, Verilog, VHDL, Perl, Python

  7d

  ASICS Design Verification Engineer (Vancouver, Markham OR Remote)

  Vancouver, BC +1

  QC

  Qualcomm Canada ULC

  2+ YOECandidates need a bachelor's degree in engineering or science and 2+ years of ASIC design or verification experience. Preferred skills include SystemVerilog and UVM testbench development, RTL design, C or C++, and Python or Perl scripting.

  SystemVerilog, UVM, Verilog, VHDL, Perl, Python

  27d

  Staff ASIC Verification Engineer, Low Power AI

  Markham, ON

  On-site

  QC

  Qualcomm Canada ULC

  4+ YOEQualcomm Canada ULC needs candidates with a relevant degree and 4+ years of ASIC work (3+ with a master's, 2+ with a PhD). Expert knowledge of Verilog, VHDL and SystemVerilog UVM is required, plus solid C skills.

  SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl

  29d

  Design Verification Engineer — Memory Subsystem (Vancouver)

  Vancouver, BC

  On-site

  QC

  Qualcomm Canada ULC

  3+ YOECandidates need a bachelor's or master's degree in an engineering or computer science field and 3 to 10 years of chip or subsystem verification experience. Hands-on skill with Verilog, SystemVerilog, UVM and assertions is required, and knowledge of memory standards such as DDR, LPDDR and HBM is preferred.

  Verilog, SystemVerilog, UVM, SystemVerilog Assertions, waveform viewers

  29d

  Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)

  Markham, ON

  On-site

  QC

  Qualcomm Canada ULC

  2+ YOECandidates need a bachelor's, master's or PhD in engineering or science with 2 to 4+ years of ASIC design or verification experience, depending on degree. Strong SystemVerilog, synthesis and design tool skills and an understanding of high-performance processor design are needed.

  SystemVerilog, VCS, Synopsys Design Compiler, Cadence, Mentor, Linting tools

• 3d

  Senior Digital ASIC Verification Engineer

  Ottawa, ON

  $112k–$179k/yrFull Time

  CC

  Ciena Canada ULC

  5+ YOECiena Canada ULC needs candidates with 5+ years of digital ASIC/SoC verification experience and a bachelor's or master's degree in electrical or computer engineering. Strong hands-on SystemVerilog and UVM skills and experience writing verification plans are essential.

  SystemVerilog, UVM, Python, Bash, Make

• 4d

  Lead Digital Verification Engineer

  Montréal, QC

  Full Time

  C

  Cadence

  Candidates need a Bachelor's degree in electrical, computer engineering or computer science, plus knowledge of verification methodologies, metric driven verification, UVM, SystemVerilog assertions and the digital design flow. A Master's degree, UVM coding experience, scripting skills and protocol knowledge such as PCIe, USB or Ethernet are preferred.

  SystemVerilog, UVM, Python, Perl, Cadence tools

• 9d

  ASIC Digital Design, Sr Staff Engineer-19314

  Markham, ON

  S

  Synopsys

  8+ YOECandidates need a BS or MS in electronics or electrical engineering with 8+ years of digital verification experience in VMM or UVM. Strong Verilog and SystemVerilog testbench skills, debugging ability, and familiarity with Python or Perl are required.

  Verilog, SystemVerilog, UVM, VMM, Jira, Confluence

  27d

  Pre-Silicon Signoff Lead

  Mississauga, ON

  S

  Synopsys

  10+ YOECandidates need an MSc or PhD in electrical or computer engineering and 10+ years of industry experience. They need deep knowledge of PCIe and Ethernet, SystemVerilog, UVM and scripting, plus proven leadership and mentoring skills.

  SystemVerilog, UVM, Python, TCL, Perl, C++

  27d

  Principal Digital Verification Engineer

  Nepean, ON

  S

  Synopsys

  12+ YOESynopsys candidates need 12+ years of verification experience with a BSc, 10+ years with an MSc, or 8+ years with a PhD. They need deep SystemVerilog and UVM skills, simulation and waveform debugging, C knowledge, assertion-based verification, and Linux scripting. Experience with LPDDR5/5X or LPDDR6 and emulation platforms is a plus.

  SystemVerilog, UVM, waveform debugger, Linux, source control, emulation platform

  27d

  ASIC Digital Design, Principal Engineer-18731

  Mississauga, ON

  S

  Synopsys

  Candidates need extensive mixed-signal ASIC or IP verification experience, strong PCIe and PCIe PHY knowledge, and hands-on SystemVerilog and UVM skills. Strong debugging and mentoring abilities are also required.

  SystemVerilog, UVM

• 14d

  Senior Verification Engineer – High Speed Coherent Interconnect Hub

  Toronto, ON

  Full Time

  NC

  NVIDIA Canada Dev. Inc.

  3+ YOECandidates need a BS or MS or equivalent experience, plus 3+ years of ASIC verification work on complex IP or SoC subsystems. Strong skills in SystemVerilog, UVM and coverage-driven verification are required.

  SystemVerilog, UVM, Python, Perl, Shell

• 15d

  ASIC Verification Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in computer or electrical engineering, plus interest in ASIC verification and digital design. Experience with SystemVerilog, C or C++, and scripting languages such as Python or Perl is an asset.

  SystemVerilog, UVM, Claude Code, Codex, Python, Perl

• 15d

  ASIC Verification Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a bachelor's or master's in computer or electrical engineering and an understanding of digital design. Experience with SystemVerilog, C or C++, and scripting such as Python or Perl is preferred.

  SystemVerilog, UVM, Claude Code, Codex, Python, Perl

• 21d

  Senior ASIC Verification Engineer

  Kanata, ON

  Full Time

  

  Myticas Consulting

  8+ YOECandidates need a related engineering degree, 8+ years of ASIC or SoC verification experience, and strong SystemVerilog, UVM and Python skills. Experience with SVA, functional coverage and formal verification tools is also needed.

  SystemVerilog, UVM, Python, Code coverage tools, Formal verification tools

• 22d

  ASIC Digital Verification Engineer

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  Candidates need knowledge of chip specifications and verification plans, plus SystemVerilog and UVM for digital verification. Experience with Synopsys or Cadence simulators, SystemVerilog assertions, functional and code coverage, and working in Unix/Linux is also needed.

  SystemVerilog, UVM, Unix, Linux

• 23d

  Digital Design Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer engineering, computer science or a related field. They need digital logic or RTL coursework or project experience, programming skills in Verilog, SystemVerilog, C/C++ or Python, and familiarity with Linux and Git.

  Verilog, SystemVerilog, Linux, Git, Python, Tcl

  23d

  DFT Engineering Intern

  Toronto, ON

  $35–$55/hr

  AL

  Astera Labs Early Career - North America 2027

  Candidates need coursework or hands-on experience in electrical or computer engineering or a related field, and an understanding of digital logic and RTL. Programming in Verilog, SystemVerilog, Python, Tcl, Perl, C or C++ is needed, plus comfort in a Linux environment.

  Verilog, SystemVerilog, Python, Tcl, Perl, Linux

  23d

  Design Verification Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer engineering or computer science. They need coding skills in SystemVerilog, C/C++ or Python, Linux and Git familiarity, and strong debugging ability.

  VCS, Verdi, DVE

• 25d

  ASIC Design Engineer, Senior

  Remote in Canada

  RemoteFull Time

  

  Positron AI

  8+ YOECandidates need a BS or MS in electrical or computer engineering with 8+ years of ASIC or SoC RTL design experience. They need deep SystemVerilog skills, front-end EDA tool expertise, and hands-on work with at least three of HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache hierarchies, or high-throughput datapaths.

  SystemVerilog, Python, Tcl, Make, UVM, cocotb

• 28d

  Principal Design Verification Engineer

  Toronto, ON

  

  indie

  7+ YOECandidates need a BSEE, BSCE or BSCS and 7+ years of design verification experience. Required skills include constrained random verification with SystemVerilog and UVM, coverage-driven verification, and strong programming in C/C++ with Python, Tcl or Perl scripting.

  SystemVerilog, UVM, C, C++, Python, Tcl

12 companies