As of November 7, 2026, Jobsy lists 9 design verification engineer jobs in Canada. The most active employers are Amazon Development Centre Canada ULC, AMD, Inc. and Astera Labs. Skills often requested: perl, python, systemverilog and electrical engineering.
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3+ YOECandidates need 3 to 10 years of digital RTL design or design verification experience, strong Verilog/SystemVerilog and UVM skills, and solid knowledge of digital design fundamentals. They also need ASIC design flow experience and the ability to write clear design documentation.
3+ YOETalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.
AMD asks for advanced ASIC functional verification experience and hands-on work on multiple projects or tapeouts. Candidates need Verilog, SystemVerilog, UVM, scripting skills, and a Bachelor's or Master's in Computer or Electrical Engineering.
4+ YOECandidates need a bachelor's degree in electrical engineering or a related field and at least 4 years of design verification experience using constrained-random simulation such as UVM. Strong debugging skills across IP, SoC and full-system levels are required.
8+ YOECandidates need a bachelor's degree in electrical engineering or a related field and 8+ years of constrained-random verification experience (such as UVM), including testbench development. Experience across IP, SoC and full-system verification, plus formal, emulation or scripting skills, is highly desired.
Candidates need hands-on hardware verification experience across multiple projects or tapeouts, with SystemVerilog, UVM, Verilog and scripting skills. A Bachelor's or Master's in Computer or Electrical Engineering is expected.
3+ YOECandidates need a bachelor's or master's degree in an engineering or computer science field and 3 to 10 years of chip or subsystem verification experience. Hands-on skill with Verilog, SystemVerilog, UVM and assertions is required, and knowledge of memory standards such as DDR, LPDDR and HBM is preferred.
5+ YOECandidates need a B.Sc. in Electrical or Computer Engineering and 5+ years of industry experience, with expert knowledge of constrained random verification (UVM, OVM, AVM or VMM) and SystemVerilog. Scripting skills in Python, TCL, Perl or C and working knowledge of Linux are also required.
Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
2+ YOECandidates need a bachelor's degree in electrical engineering or a related field and 2 to 5 years of verifying complex chips. Hands-on SystemVerilog, UVM and C/C++ experience, including C/C++ integration with SystemVerilog, is required, as is authorization to work in Canada.