FrontEnd CMA (CAD) Engineer
Toronto, ONARM
Candidates need experience in ASIC/SoC build or front-end CAD, strong Python and Tcl skills, and knowledge of RTL, Verilog/SystemVerilog and verification methods such as Lint, CDC and formal. They also need experience building production CAD flows, a degree in electrical or computer engineering or computer science (or equivalent experience), and an AI-first approach to automation.
Python, Tcl, Shell, Linux, Verilog, SystemVerilog
Senior PCIe Design Engineer
Toronto, ONARM
5+ YOEArm needs candidates with a Bachelor's or Master's degree in a related engineering or computer science field and 5+ years of SoC or compute subsystem design experience. Candidates need Verilog, PCIe, CXL or Ethernet integration experience and scripting skills in Perl or Python.
Verilog HDL, Perl, Python
Staff PCIe Design Engineer
Toronto, ONARM
10+ YOECandidates need a Bachelor's or Master's degree in computer science or electrical or computer engineering, 10+ years designing complex SoCs or compute subsystems, and strong Verilog and digital design skills. Experience with PCIe, CXL, UCIe or Ethernet subsystems and static design checks is required.
Verilog HDL, Perl, Python
Senior Design Engineer - Security IP
Toronto, ONARM
ARM needs a degree in computer science or electrical or computer engineering and a proven record of leading hardware design of compute, multimedia or security subsystems. Candidates need hands-on experience with Verilog RTL, cryptography, secure boot, SoC architecture and scripting.
Verilog, SystemVerilog, Perl, Python, TCL, UPF