DV - Staff (+) Verification Engineer - AMS modeling
CanadaOn-siteFull Time
E
Eliyan
5+ YOECandidates need 5+ years of relevant experience, a BS in EE or a related field, deep analog design expertise, and experience verifying mixed-signal IPs. Knowledge of SystemVerilog, test environments and assertion coding is required.
SystemVerilog, UVM, vc-formal, Python, Perl, Tcl