“SystemVerilog” jobs in Canada – Page 3

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• 24d

  Summer 2027 Long Term ASIC Verification Engineering Intern/ Co-Op

  Ottawa, ON

  AI

  AMD, Inc.

  Candidates need to be 3rd or 4th year Computer Engineering or Computer Science students with digital design knowledge, object-oriented coding skills, and experience with SystemVerilog, C or C++. Python, Perl or other scripting experience and AI tools experience are assets, and valid work authorization is required.

  SystemVerilog, UVM, C, C++, Python, Perl

  25d

  RTL/Firmware Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a Bachelor's or Master's in computer engineering, electrical engineering, computer science or a related field. Embedded C/C++, reading Verilog or SystemVerilog, Python scripting and analytical problem-solving are preferred.

  Verilog, SystemVerilog, Git, Perforce, Jenkins, Python

  25d

  SoC Design Lead, Microarchitecture and Design Methodology

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need strong computer architecture and digital design foundations, plus knowledge of STA, clocks and power optimization. Verilog or SystemVerilog experience with UVM is preferred, along with strong communication, analytical and teamwork skills.

  Verilog, SystemVerilog, UVM

  25d

  Principal ASIC Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a track record of leading ASIC or silicon designs through multiple product tape-outs, plus deep RTL and microarchitecture experience. Strong communication skills and the ability to lead technical reviews are also required.

  Verilog, SystemVerilog, Python, Perl, Tcl

  25d

  Design Verification Lead

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a bachelor's or master's degree in electrical or computer engineering, computer science or a related field, plus UVM and SystemVerilog experience and knowledge of high-speed protocols such as PCIe, CXL or Ethernet. Scripting in Python or Perl and technical leadership skills are also needed.

  SystemVerilog, Verilog, UVM, Python, Perl

• 24d

  Sr. Engineer, Staff Analog Design

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  10+ YOECandidates need a Master's or PhD in Electrical Engineering, 10+ years in analog/mixed-signal CMOS design, and PLL design experience. Cadence tools and lab characterization experience are also required.

  Cadence, SystemVerilog, Verilog-A

  24d

  Engineer, Staff Analog Design

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  6+ YOECandidates need a Master's or PhD in Electrical Engineering and 6+ years of analog or mixed-signal IC design, including PLL design, CMOS or BiCMOS experience, and hands-on lab characterization.

  Cadence, SystemVerilog, Verilog-A, AMS

  24d

  Co-op ASIC Digital Verification Engineer

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  Candidates need good academic standing, object-oriented coding skills and strong problem-solving ability. Knowledge of Verilog, SystemVerilog, UVM, Python or Tcl is an asset, and English proficiency is required.

  Verilog, SystemVerilog, UVM, Python, Tcl

  24d

  ASIC Digital Verification Engineer

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  Candidates need knowledge of chip specifications and verification plans, plus SystemVerilog and UVM for digital verification. Experience with Synopsys or Cadence simulators, SystemVerilog assertions, functional and code coverage, and working in Unix/Linux is also needed.

  SystemVerilog, UVM, Unix, Linux

• 24d

  Staff Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  9+ YOECandidates need a Bachelor's or Master's in computer science, electrical engineering or a related field, plus at least 9 years of ASIC design verification experience. Strong SystemVerilog and UVM skills and advanced debugging are required.

  SystemVerilog, UVM, EDA tools

  24d

  Senior Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  3+ YOETalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.

  SystemVerilog, UVM, Python, Perl, C/C++, GNU Make

  24d

  Senior ASIC Verification Engineer

  Ottawa, ON

  Hybrid

  T

  Talentlab

  Candidates need an engineering degree, proven digital verification experience, and knowledge of formal verification and functional coverage. They should also be proficient in a programming language such as Python or C/C++ and be based in Ottawa.

  SystemVerilog, UVM, Python, C++, SystemC, Make

• 24d

  DFT & Post-Silicon Validation

  Gatineau, QC

  HybridFull Time

  

  TechBiz Global GmbH

  Candidates need a degree in computer science, electrical engineering or a related field and proven experience taping out high-performance SoCs or SiPs for mass production. They also need strong post-silicon test and yield analysis skills, and RTL and testbench coding in SystemVerilog and Verilog.

  Tessent, SystemVerilog, Verilog, Tcl, Python3, Shell

• 25d

  Digital Design Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer engineering, computer science or a related field. They need digital logic or RTL coursework or project experience, programming skills in Verilog, SystemVerilog, C/C++ or Python, and familiarity with Linux and Git.

  Verilog, SystemVerilog, Linux, Git, Python, Tcl

  25d

  DFT Engineering Intern

  Toronto, ON

  $35–$55/hr

  AL

  Astera Labs Early Career - North America 2027

  Candidates need coursework or hands-on experience in electrical or computer engineering or a related field, and an understanding of digital logic and RTL. Programming in Verilog, SystemVerilog, Python, Tcl, Perl, C or C++ is needed, plus comfort in a Linux environment.

  Verilog, SystemVerilog, Python, Tcl, Perl, Linux

  25d

  Design Verification Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer engineering or computer science. They need coding skills in SystemVerilog, C/C++ or Python, Linux and Git familiarity, and strong debugging ability.

  VCS, Verdi, DVE

• 26d

  Design Verification Lead

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong UVM and SystemVerilog skills, and experience verifying high-speed protocols such as PCIe, CXL or Ethernet. Technical leadership, mentoring and scripting in Python or Perl are preferred.

  SystemVerilog, Verilog, UVM, Python, Perl

• 27d

  ASIC Design Engineer, Senior

  Remote in Canada

  RemoteFull Time

  

  Positron AI

  8+ YOECandidates need a BS or MS in electrical or computer engineering with 8+ years of ASIC or SoC RTL design experience. They need deep SystemVerilog skills, front-end EDA tool expertise, and hands-on work with at least three of HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache hierarchies, or high-throughput datapaths.

  SystemVerilog, Python, Tcl, Make, UVM, cocotb

• 28d

  Senior Firmware Developer

  Waterloo, ON

  Full Time

  

  onsemi: With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety,…

  3+ YOECandidates need a Bachelor's or Master's degree in an engineering discipline and 3-5 years of embedded firmware experience. Strong embedded C, microprocessor and communication protocol knowledge (UART, I2C, SPI, USB) and experience with AI-assisted development tools are required.

  Git, JIRA, FPGA, oscilloscope, logic analyzer, hardware debugger

• 28d

  FPGA Designer

  Remote in Canada

  $125k–$160k/yrRemoteFull Time

  

  Fidus Systems: Founded in 2001, Fidus Systems is a premier electronic system design and development company with specialized expertise in FPGA design, embedded…

  5+ YOECandidates need at least 5 years of FPGA design experience using RTL, Verilog or VHDL, with knowledge of video, communications and DSP systems. Fidus Systems also requires Xilinx or Altera tool experience, a degree in engineering, strong English communication skills, and the ability to pass Canadian controlled-goods security screening.

  Xilinx Vivado, Altera Quartus, ModelSim, Verilog, VHDL, SystemVerilog

• 29d

  Pre-Silicon Signoff Lead

  Mississauga, ON

  S

  Synopsys

  10+ YOECandidates need an MSc or PhD in electrical or computer engineering and 10+ years of industry experience. They need deep knowledge of PCIe and Ethernet, SystemVerilog, UVM and scripting, plus proven leadership and mentoring skills.

  SystemVerilog, UVM, Python, TCL, Perl, C++

  29d

  Principal Digital Verification Engineer

  Nepean, ON

  S

  Synopsys

  12+ YOESynopsys candidates need 12+ years of verification experience with a BSc, 10+ years with an MSc, or 8+ years with a PhD. They need deep SystemVerilog and UVM skills, simulation and waveform debugging, C knowledge, assertion-based verification, and Linux scripting. Experience with LPDDR5/5X or LPDDR6 and emulation platforms is a plus.

  SystemVerilog, UVM, waveform debugger, Linux, source control, emulation platform

  29d

  ASIC Digital Design, Principal Engineer-18731

  Mississauga, ON

  S

  Synopsys

  Candidates need extensive mixed-signal ASIC or IP verification experience, strong PCIe and PCIe PHY knowledge, and hands-on SystemVerilog and UVM skills. Strong debugging and mentoring abilities are also required.

  SystemVerilog, UVM

  29d

  ASIC Digital Verification, Sr. Manager

  Mississauga, ON

  S

  Synopsys

  15+ YOECandidates need a BS or MS in EE, EC or VLSI with 15+ years of IP or SoC verification experience, and strong team leadership. They must know Verilog, SystemVerilog and UVM, and Perl or Python automation. PCIe and Ethernet knowledge is an asset.

  Verilog, SystemVerilog, UVM, Perl, Python

10 companies