Ingénieur principal du personnel technique – Conception analogique/ Senior Technical Staff Engineer - Analog Design
Montréal, QCFull Time
MS
MCHP Semiconductor Canada ULC
10+ YOEMaîtrise ou doctorat en génie électrique; Plus de 10 ans d’expérience en circuits intégrés analogiques et mixtes; Expérience en PLL/DLL, ADC/DAC et interfaces E/S haute vitesse
Cadence IC, Verilog-A, Skill, Python, Perl, Tcl
Senior Manager-Design Engineering
Burnaby, BC +2Full Time
MS
MCHP Semiconductor Canada ULC
12+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering, 12+ years of related experience and proven experience leading engineering teams. Strong coaching skills, debugging ability and Verilog or VHDL design experience are required; SOC, communication protocols, Synopsys or Cadence tools and 28nm process experience are assets.
Verilog, VHDL, Synopsys, Cadence