“SystemVerilog” jobs in Canada – Page 6

No matching filters. Try another name.

Results

• 1mo

  Mixed Signal Design Engineer

  Ottawa, ON

  $93k–$149k/yrFull Time

  CC

  Ciena Canada ULC

  Ciena Canada ULC needs a degree in electrical or computer engineering, computer science or a related science. Candidates need CMOS or BiCMOS design experience and skill with Cadence, Synopsys and Siemens EDA tools, plus SystemVerilog, Verilog-AMS, Python and C/C++.

  Cadence Virtuoso, Cadence Xcelium, Cadence AMS, Synopsys VCS, Synopsys StarRC, Siemens Questa

• 1mo

  DV - Staff (+) Verification Engineer - AMS modeling

  Canada

  On-siteFull Time

  E

  Eliyan

  5+ YOECandidates need 5+ years of relevant experience, a BS in EE or a related field, deep analog design expertise, and experience verifying mixed-signal IPs. Knowledge of SystemVerilog, test environments and assertion coding is required.

  SystemVerilog, UVM, vc-formal, Python, Perl, Tcl

  1mo

  Digital - Staff Digital Design Engineer - PHY

  Canada

  On-siteFull Time

  E

  Eliyan

  8+ YOEEliyan needs 8+ years of digital frontend design with 4+ years in PHY or high-speed interfaces, and 3+ tapeouts as design lead at 7nm or below. Candidates need expert SystemVerilog, synthesis, CDC and UCIe or DDR/SerDes knowledge.

  SystemVerilog, Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, UPF, SDC

  1mo

  Digital - Digital Design Engineer (title will reflect experience)

  Canada

  On-siteFull Time

  E

  Eliyan

  5+ YOECandidates need a degree in electrical engineering or a related field and 5+ years of high-speed digital design experience. They need strong SystemVerilog and synthesis skills, knowledge of IEEE 802.3 Ethernet standards, and startup experience.

  SystemVerilog, SDC constraints

  1mo

  Digital - ASIC Design Automation & Integration Engineer

  Canada

  On-siteFull Time

  E

  Eliyan

  5+ YOEEliyan needs candidates with a relevant engineering degree and five or more years in ASIC or SoC design or design automation. Candidates must know lint, CDC and synthesis tools, SystemVerilog, Python, Tcl, Git, Linux and CI/CD pipelines, and be authorized to work in the United States or Canada.

  SpyGlass, QuestaLint, Genus, Fusion Compiler, Jenkins, Git

• 1mo

  Staff Design Verification Engineer, AI HW

  Toronto, ON

  

  Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.

  Candidates need experience with modern verification methods and strong SystemVerilog skills, plus Linux scripting in Python or Bash. They should be comfortable with coverage-driven verification and debugging across RTL, testbenches and workloads.

  SystemVerilog, Python, Bash, Linux

  1mo

  Design Verification Lead, AI Hardware

  Toronto, ON

  

  Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.

  Candidates need experience leading ASIC or SoC verification through complex chip releases, plus knowledge of AI and machine learning hardware. They should be hands-on with UVM, SystemVerilog and cocotb, and able to plan tests that work from simulation to FPGA to silicon.

  UVM, SystemVerilog, cocotb, FPGA

• 1mo

  CPU Verification Engineer

  Markham, ON

  HybridFull Time

  

  NUVACORE

  4+ YOECandidates need a degree in electrical or computer engineering or computer science (or equivalent experience), 4+ years (Senior) or 15+ years (Principal) of design verification, CPU microarchitecture knowledge, and skill in C/C++ or SystemVerilog plus Python.

  SystemVerilog, C/C++, Python, Perl, FPGA

  1mo

  CPU Architecture Verification Engineer

  Markham, ON

  HybridFull Time

  

  NUVACORE

  4+ YOECandidates need a degree in electrical or computer engineering, computer science or equivalent experience, plus 4+ years (Senior) or 15+ years (Principal) of design verification. They need strong CPU architecture knowledge, one modern ISA (x86, ARM or RISC-V), and skill in C/C++/Rust or SystemVerilog with Python.

  SystemVerilog, Python, Perl, FPGA

• 1mo

  Senior FPGA Designer

  Montréal, QC

  HybridFull Time

  E

  Exegy

  5+ YOEDiplôme en génie électronique, électrique ou informatique; Cinq ans ou plus d'expérience en conception FPGA; Maîtrise avancée du VHDL et/ou du Verilog

  Vivado, Git, Jenkins, Python, Linux

• 1mo

  Senior Digital Design Engineer

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  2+ YOECandidates need a bachelor's degree in electrical or electronics engineering, 2 to 5 years of digital design experience on complex chips, and hands-on SystemVerilog or Verilog RTL skills. PCIe or Ethernet IP experience and Python or Perl scripting are also required, and candidates must be authorized to work in Canada.

  SystemVerilog, Verilog, Synopsys, Cadence, Python, Perl

  1mo

  Senior Design Verification Engineer

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  2+ YOECandidates need a bachelor's degree in electrical engineering or a related field and 2 to 5 years of verifying complex chips. Hands-on SystemVerilog, UVM and C/C++ experience, including C/C++ integration with SystemVerilog, is required, as is authorization to work in Canada.

  SystemVerilog, UVM, C/C++, Python, Perl, FPGA emulation platform

• 1mo

  Staff/Sr. Staff Design Verification Engineer

  Toronto, ON

  

  Lightmatter

  8+ YOECandidates need a bachelor's degree in an engineering field and at least 8 years of design verification and SystemVerilog experience. Python experience of 2 or more years, expertise with the UVM library and experience with Xcelium, ModelSim, Questa or VCS are also required.

  Xcelium, ModelSim, Questa, VCS, UVM, SystemVerilog

7 companies