ASIC Physical Design Engineer, Senior
Remote in CanadaPositron AI
5+ YOECandidates need 5 to 8 years of physical design experience and at least one advanced-node tapeout. Strong Innovus or ICC2 skills and knowledge of timing, power and clock tree synthesis are required.
Innovus, ICC2, Tempus, PrimeTime, Voltus, RedHawk
ASIC Physical Design Engineer - DFT, Senior
Remote in CanadaPositron AI
8+ YOEPositron AI needs 8+ years of ASIC development with several production tapeouts, deep DFT experience, and hands-on Siemens Tessent. Candidates also need Verilog/SystemVerilog RTL skills, synthesis and gate-level verification, and scripting in Python, Tcl or Perl.
Siemens Tessent, Verilog, SystemVerilog, Python, Tcl, Perl
ASIC Design Engineer, Senior
Remote in CanadaPositron AI
8+ YOECandidates need a BS or MS in electrical or computer engineering with 8+ years of ASIC or SoC RTL design experience. They need deep SystemVerilog skills, front-end EDA tool expertise, and hands-on work with at least three of HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache hierarchies, or high-throughput datapaths.
SystemVerilog, Python, Tcl, Make, UVM, cocotb
Physical Design Engineer - Synth, Senior
Remote in CanadaPositron AI
8+ YOECandidates need 8+ years of ASIC implementation experience, including at least two tapeouts, and strong synthesis and timing-closure experience on large designs. Expertise with Genus or Design Compiler, SDC constraints, Tcl and Python scripting, and advanced process nodes (7nm and below preferred) is required.
Cadence Genus, Synopsys Design Compiler, Tcl, Python