SOC Design Engineer
Markham, ON +2On-site
Qualcomm Canada ULC
4+ YOECandidates need a degree in science or engineering and 4+ years of ASIC design, verification or integration work, with strong digital front-end design skills in Verilog, SystemVerilog and VHDL. Experience with power domains, clock domain crossing, low-power design and chip design tools is needed.
Spyglass, Design Compiler, Cadence LEC, Perl, TCL
Camera Design Engineer
Vancouver, BCOn-site
Qualcomm Canada ULC
3+ YOECandidates need a bachelor's, master's or PhD in a computer, electrical or related engineering field, with 4 to 2 years of hardware or related experience depending on degree. Verilog or VHDL RTL design, design verification and bus protocol experience are key.
Verilog, VHDL, TCL, Perl, Python