Principal Analog Mixed Signal Designer - 19497
Mississauga, ONSynopsys
5+ YOECandidates need a PhD with 5+ years or a Master's with 8+ years of hands-on analog IC design experience. Strong CMOS skills, detailed SerDes sub-circuit design experience and SPICE simulation expertise are required.
SPICE simulators, Verilog-A, schematic entry tools, physical layout tools, MATLAB, Python
Sr Manager or Principal Engineer for Firmware Development - 19315
Markham, ONSynopsys
10+ YOECandidates need a Bachelor's, Master's or PhD in computer or electrical engineering, or equivalent experience, with 10+ years in a related field. They need strong skills in digital logic and firmware development, proficiency in C, Verilog and SystemVerilog/UVM, and experience leading complex projects.
Verilog, UVM, C, Python, Perl, Bash
ASIC Digital Design, Architect
Markham, ONSynopsys
10+ YOECandidates need a master's degree or equivalent experience and 10+ years of digital ASIC design, ideally in high-speed or mixed-signal work. They need strong Verilog or VHDL skills, clock domain crossing knowledge, synthesis and DFT experience, and experience working with verification teams.
Verilog, VHDL, synthesis tools, DFT tools
Project Engineering Management, Principal Engineer - 18617
Mississauga, ONSynopsys
8+ YOECandidates need an engineering or applied science degree (or equivalent) and 8+ years of semiconductor experience. Strong project management skills, customer communication experience, and knowledge of SOC, ASIC, Silicon IP, PCIe and Ethernet are expected.
Linux