Senior Emulation Performance Methodology & Debug Engineer
Markham, ONQualcomm Technologies, Inc.
4+ YOECandidates need a bachelor's, master's or PhD in a science or engineering field with 4+, 3+ or 2+ years of ASIC design or verification experience respectively. Preferred: 5+ years in emulation and silicon environments, plus Verilog/SystemVerilog, C, Python, TCL and FPGA timing closure skills.
Veloce, Palladium, FPGA prototyping, JTAG debugger, Xilinx FPGA, Intel FPGA
SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)
Markham, ONQualcomm Technologies, Inc.
7+ YOEQualcomm needs a candidate with 7+ years of silicon validation or platform bring-up experience and deep knowledge of NoCs, AXI, memory hierarchy, power modes and debug. A degree in engineering or computer science is required, with embedded C/C++, Python and assembly skills.
JTAG debugger, Perfmon, kernel debugger, emulation platform
System Validation Lead (Premium Mobile Platforms)
Markham, ONQualcomm Technologies, Inc.
8+ YOECandidates need 8+ years of SoC validation, bring-up, or system software experience, deep knowledge of modern SoC architectures such as ARM CPUs, memory and interconnects, and proven pre- and post-silicon validation and debug skills. Leadership of geographically distributed teams is required.
Veloce, RUMI, FPGA
SoC Infrastructure/NoC, Power & Performance Validation Engineer
Markham, ONQualcomm Technologies, Inc.
5+ YOECandidates need several years of ASIC design, validation or verification experience, with a strong grasp of on-chip interconnects, performance and power. Strong programming in C, C++, Python and assembly, plus JTAG and kernel debugging, are expected.
JTAG debuggers, kernel debuggers, state dump scripts, Python, C, C++