Technical Staff Engineer - Design
Burnaby, BCMCHP Semiconductor Canada ULC
12+ YOECandidates need a B.S. in electrical engineering with 12+ years of related experience, hands-on pad ring and bump map work for advanced SoC designs, and knowledge of IO standards such as SerDes, DDR, PCIe and CXL. Scripting skills in Tcl or Python are required.
Orbit IO, ISP, Tcl, Python, Verilog, SVN
Software Engineer
Toronto, ONMCHP Semiconductor Canada ULC
7+ YOECandidates need a degree in computer science or electrical or computer engineering, 7+ years of software experience, strong C/C++ skills and at least 2 years working with LLVM/MLIR. A solid grasp of digital design and algorithms is also required.
LLVM, MLIR, Git, Python, TCL, Bash
Senior SoC Design Engineer
Burnaby, BCMCHP Semiconductor Canada ULC
3+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering and 3 to 5 years of related experience, including RTL design in SystemVerilog and Verilog. Experience with ASIC design flows, synthesis, static timing analysis and PCI-Express is valued.
Synopsys Design Compiler, Cadence Incisive, Verilog, Perl, Python, Tcl
Senior Engineer II - Physical Design
Burnaby, BCMCHP Semiconductor Canada ULC
7+ YOECandidates need a 4-year Electrical or Electronics Engineering degree and 7.5+ years of ASIC development experience. They need hands-on skill in synthesis, static timing and place and route for high-performance designs, plus Python, Perl or TCL scripting.
Verilog, VHDL, Python, Perl, TCL
Senior Manager-Design Engineering
Burnaby, BC +2MCHP Semiconductor Canada ULC
12+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering, 12+ years of related experience and proven experience leading engineering teams. Strong coaching skills, debugging ability and Verilog or VHDL design experience are required; SOC, communication protocols, Synopsys or Cadence tools and 28nm process experience are assets.
Verilog, VHDL, Synopsys, Cadence