“ASIC” jobs in Canada – Page 2

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• 24d

  ASIC Digital Verification Engineer

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  Candidates need knowledge of chip specifications and verification plans, plus SystemVerilog and UVM for digital verification. Experience with Synopsys or Cadence simulators, SystemVerilog assertions, functional and code coverage, and working in Unix/Linux is also needed.

  SystemVerilog, UVM, Unix, Linux

  24d

  Co - op ASIC Systems Engineer

  Ottawa, ON

  $24–$26/hr

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  SiTime needs a third-year or higher electrical engineering student with hands-on lab experience, Python programming skills, and soldering ability down to 0201 size. Transmission line theory and serial communication knowledge are assets.

  oscilloscope, frequency counter, signal generator, GitLab, Python

• 24d

  Senior ASIC Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  2+ YOECandidates need a Bachelor's in electrical engineering (a Master's is preferred) and 2+ years supporting complex SoC silicon for server, storage or networking. They must have hands-on UVM, C/C++ and System Verilog experience, plus experience with third-party protocol VIPs such as PCIe, Ethernet and DDR.

  System Verilog, UVM, Perl, Python

  24d

  ASIC Physical Designer

  Ontario

  T

  Talentlab

  Candidates need experience with physical design CAD flows and design verification, and proficiency in DRC, LVS and debug methods. Hands-on Cadence Virtuoso, PERL or Shell scripting, and Unix/Linux skills are preferred, along with a bachelor's degree in a relevant field.

  Cadence Virtuoso, PERL, Shell, Unix/Linux

  24d

  Senior ASIC Verification Engineer

  Ottawa, ON

  Hybrid

  T

  Talentlab

  Candidates need an engineering degree, proven digital verification experience, and knowledge of formal verification and functional coverage. They should also be proficient in a programming language such as Python or C/C++ and be based in Ottawa.

  SystemVerilog, UVM, Python, C++, SystemC, Make

  24d

  Staff ASIC Design Engineer – AI/ML Hardware IP

  Toronto, ON

  T

  Talentlab

  5+ YOECandidates need at least 5 years of hands-on ASIC design experience and strong skills in Verilog, SystemVerilog, and logic synthesis. A degree in electrical or computer engineering is required, and candidates must be legally authorized to work on-site in Canada.

  Verilog, SystemVerilog, Design Compiler, PrimeTime, Formality, Spyglass

  24d

  Senior Staff ASIC Design Egineer - AI/ML Hardware IP

  Toronto, ON

  T

  Talentlab

  6+ YOECandidates need six or more years of ASIC design and integration experience (or a Master's plus five years, or a PhD plus four), strong Verilog/SystemVerilog skills, and experience owning complex SoC blocks. A Bachelor's, Master's or PhD in electrical engineering or a related field is required, and the candidate must be legally authorized to work in Canada.

  Verilog, SystemVerilog, VCS, Verdi, Questa, Xcelium

• 25d

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

  25d

  Principal ASIC Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a track record of leading ASIC or silicon designs through multiple product tape-outs, plus deep RTL and microarchitecture experience. Strong communication skills and the ability to lead technical reviews are also required.

  Verilog, SystemVerilog, Python, Perl, Tcl

• 27d

  ASIC Physical Design Engineer, Senior

  Remote in Canada

  RemoteFull Time

  

  Positron AI

  5+ YOECandidates need 5 to 8 years of physical design experience and at least one advanced-node tapeout. Strong Innovus or ICC2 skills and knowledge of timing, power and clock tree synthesis are required.

  Innovus, ICC2, Tempus, PrimeTime, Voltus, RedHawk

  27d

  ASIC Physical Design Engineer - Power, Senior

  Remote in Canada

  RemoteFull Time

  

  Positron AI

  8+ YOECandidates need 8+ years of ASIC design experience with a strong power focus, hands-on low-power design and UPF/CPF experience, and proficiency with PrimePower, Joules and Tcl or Python. Advanced process node experience and a track record of meeting power targets on production silicon are required.

  PrimePower, Joules, Tcl, Python, UPF, CPF

  27d

  ASIC Physical Design Engineer - DFT, Senior

  Remote in Canada

  RemoteFull Time

  

  Positron AI

  8+ YOEPositron AI needs 8+ years of ASIC development with several production tapeouts, deep DFT experience, and hands-on Siemens Tessent. Candidates also need Verilog/SystemVerilog RTL skills, synthesis and gate-level verification, and scripting in Python, Tcl or Perl.

  Siemens Tessent, Verilog, SystemVerilog, Python, Tcl, Perl

  27d

  ASIC Design Engineer, Senior

  Remote in Canada

  RemoteFull Time

  

  Positron AI

  8+ YOECandidates need a BS or MS in electrical or computer engineering with 8+ years of ASIC or SoC RTL design experience. They need deep SystemVerilog skills, front-end EDA tool expertise, and hands-on work with at least three of HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache hierarchies, or high-throughput datapaths.

  SystemVerilog, Python, Tcl, Make, UVM, cocotb

  27d

  ASIC Architect, Principal (AI Inference)

  Remote in Canada

  RemoteFull Time

  

  Positron AI

  15+ YOECandidates need 15+ years of ASIC architecture experience, deep expertise in AI accelerators and high-performance SoCs, and hands-on work with memory and interconnect performance models. Strong hardware/software co-design and excellent communication skills are required.

  Machine learning, ML, Communication skills, Firmware, Research

• 29d

  ASIC Physical Design, Sr Staff Engineer - 16724

  Nepean, ON

  S

  Synopsys

  9+ YOECandidates need 9+ years of ASIC physical design experience on complex SoC or test chip projects at advanced nodes. They must know the full physical design flow and tools such as Design Compiler, PrimeTime, IC Compiler II, Calibre and RedHawk, and must be authorized to work in the USA.

  Design Compiler, PrimeTime, IC Compiler II, ICV, Calibre, RedHawk

  29d

  ASIC Digital Design, Architect

  Markham, ON

  S

  Synopsys

  10+ YOECandidates need a master's degree or equivalent experience and 10+ years of digital ASIC design, ideally in high-speed or mixed-signal work. They need strong Verilog or VHDL skills, clock domain crossing knowledge, synthesis and DFT experience, and experience working with verification teams.

  Verilog, VHDL, synthesis tools, DFT tools

  29d

  ASIC Digital Design, Principal Engineer-18731

  Mississauga, ON

  S

  Synopsys

  Candidates need extensive mixed-signal ASIC or IP verification experience, strong PCIe and PCIe PHY knowledge, and hands-on SystemVerilog and UVM skills. Strong debugging and mentoring abilities are also required.

  SystemVerilog, UVM

  29d

  ASIC Digital Verification, Sr. Manager

  Mississauga, ON

  S

  Synopsys

  15+ YOECandidates need a BS or MS in EE, EC or VLSI with 15+ years of IP or SoC verification experience, and strong team leadership. They must know Verilog, SystemVerilog and UVM, and Perl or Python automation. PCIe and Ethernet knowledge is an asset.

  Verilog, SystemVerilog, UVM, Perl, Python

• 29d

  Staff ASIC Verification Engineer, Low Power AI

  Markham, ON

  On-site

  

  Qualcomm Canada ULC

  4+ YOEQualcomm Canada ULC needs candidates with a relevant degree and 4+ years of ASIC work (3+ with a master's, 2+ with a PhD). Expert knowledge of Verilog, VHDL and SystemVerilog UVM is required, plus solid C skills.

  SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl

  1mo

  Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)

  Markham, ON

  On-site

  

  Qualcomm Canada ULC

  2+ YOECandidates need a bachelor's, master's or PhD in engineering or science with 2 to 4+ years of ASIC design or verification experience, depending on degree. Strong SystemVerilog, synthesis and design tool skills and an understanding of high-performance processor design are needed.

  SystemVerilog, VCS, Synopsys Design Compiler, Cadence, Mentor, Linting tools

  1mo

  Senior ASIC Design Verification Engineer, Compute DSP/AI Processors (multiple levels)

  Markham, ON

  On-site

  

  Qualcomm Canada ULC

  4+ YOECandidates need an engineering degree and, for senior roles, several years of ASIC design or verification experience. Strong skills in UVM, SystemVerilog, digital logic and scripting in Python or CShell are expected, along with good problem solving and communication.

  SystemVerilog, UVM, Python, CShell

• 1mo

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's in computer or electrical engineering, and strong Verilog or SystemVerilog RTL design skills. Experience delivering ASIC or FPGA products, plus networking or high-speed interface knowledge, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

  1mo

  Summer 2027 Long Term ASIC Verification Engineering Intern/ Co-Op

  Ottawa, ON

  AM

  Advanced Micro Devices, Inc

  Candidates need to be 3rd or 4th year Computer Engineering or Computer Science students with digital design knowledge, object-oriented coding skills, and experience with SystemVerilog, C or C++. Experience with AI tools is required, and Python, Perl or other scripting languages are an asset.

  SystemVerilog, UVM, C++, Python, Perl

  1mo

  Principal ASIC Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a track record of leading ASIC or silicon designs through multiple tape-outs, plus deep RTL and microarchitecture skills. A bachelor's degree in an engineering or computer field is preferred, and a master's or PhD is desired.

  Verilog, SystemVerilog, Python, Perl, Tcl

7 companies