“ASIC” jobs in Canada

No matching filters. Try another name.

Results

• 23d

  ASIC Design and ASIC Design Verification roles (Hardware engineers) - 3 Vacancies

  Toronto, ON

  On-siteContract

  SC

  system canada technologies

  Candidates need hardware engineering experience in ASIC design or verification.

• 2d

  Senior Digital ASIC Verification Engineer

  Ottawa, ON

  $112k–$179k/yrFull Time

  CC

  Ciena Canada ULC

  5+ YOECiena Canada ULC needs candidates with 5+ years of digital ASIC/SoC verification experience and a bachelor's or master's degree in electrical or computer engineering. Strong hands-on SystemVerilog and UVM skills and experience writing verification plans are essential.

  SystemVerilog, UVM, Python, Bash, Make

  7d

  ASIC Engineer Intern

  Ottawa, ON

  $25.50–$35/hrFull Time

  CC

  Ciena Canada ULC

  Candidates need programming experience in Java, Python, TCL, Skill/Ocean or SystemVerilog, and familiarity with Linux. Experience with ASIC or FPGA work, debugging skills and Agile, JIRA, Confluence or Git are assets.

  SystemVerilog, UVM, Python, TCL, Skill/Ocean, Java

• 8d

  ASIC Digital Design, Sr Staff Engineer-19314

  Markham, ON

  S

  Synopsys

  8+ YOECandidates need a BS or MS in electronics or electrical engineering with 8+ years of digital verification experience in VMM or UVM. Strong Verilog and SystemVerilog testbench skills, debugging ability, and familiarity with Python or Perl are required.

  Verilog, SystemVerilog, UVM, VMM, Jira, Confluence

• 10d

  Senior Analog ASIC Design Engineer

  Toronto, ON

  HybridFull Time

  

  Xanadu: is a Canadian quantum technology company, and one of the world's leading photonic quantum hardware providers.

  5+ YOEXanadu needs 5+ years of analog or mixed-signal IC design experience, with a track record of taking designs to tested silicon. Candidates need deep experience with high-speed or high-voltage circuits, multiple process nodes, and Cadence tools, plus a Bachelor's or Master's in electrical engineering.

  Cadence

  10d

  Principal Analog ASIC Design Engineer

  Remote in Canada

  RemoteFull Time

  

  Xanadu: is a Canadian quantum technology company, and one of the world's leading photonic quantum hardware providers.

  10+ YOECandidates need 10+ years of analog or mixed-signal IC design experience, including leading complex tape-outs to silicon. They also need deep analog circuit design skills, multi-node process experience, and Cadence EDA mastery.

  Cadence

• 10d

  Sr. Engineer, Mixed Signal ASIC Systems

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  3+ YOECandidates need 3 to 5 years of experience in high-frequency signals, timing or embedded systems, a bachelor's degree in electrical engineering or a related field, and strong English. Hands-on lab experience with oscilloscopes and power supplies and knowledge of serial protocols are needed.

  oscilloscope, frequency counter, signal generator, Python, GitLab, SCPI

  22d

  Co-op ASIC Digital Verification Engineer

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  Candidates need good academic standing, object-oriented coding skills and strong problem-solving ability. Knowledge of Verilog, SystemVerilog, UVM, Python or Tcl is an asset, and English proficiency is required.

  Verilog, SystemVerilog, UVM, Python, Tcl

  22d

  ASIC Digital Verification Engineer

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  Candidates need knowledge of chip specifications and verification plans, plus SystemVerilog and UVM for digital verification. Experience with Synopsys or Cadence simulators, SystemVerilog assertions, functional and code coverage, and working in Unix/Linux is also needed.

  SystemVerilog, UVM, Unix, Linux

  22d

  Co - op ASIC Systems Engineer

  Ottawa, ON

  $24–$26/hr

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  SiTime needs a third-year or higher electrical engineering student with hands-on lab experience, Python programming skills, and soldering ability down to 0201 size. Transmission line theory and serial communication knowledge are assets.

  oscilloscope, frequency counter, signal generator, GitLab, Python

• 14d

  ASIC Verification Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in computer or electrical engineering, plus interest in ASIC verification and digital design. Experience with SystemVerilog, C or C++, and scripting languages such as Python or Perl is an asset.

  SystemVerilog, UVM, Claude Code, Codex, Python, Perl

  16d

  ASIC Design Engineer, PCIe IP Enablement

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need hands-on ASIC hardware design experience with end-to-end ownership of complex digital IP through tape-out. Strong RTL and Verilog skills, low-power design knowledge and a Bachelor's or Master's in electrical or computer engineering are preferred.

  Verilog HDL, UPF, CPF, Lint tools, CDC tools, Synthesis tools

• 14d

  ASIC Verification Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a bachelor's or master's in computer or electrical engineering and an understanding of digital design. Experience with SystemVerilog, C or C++, and scripting such as Python or Perl is preferred.

  SystemVerilog, UVM, Claude Code, Codex, Python, Perl

  16d

  ASIC Design Engineer, PCIe IP Enablement

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need hands-on ASIC hardware design experience with end-to-end ownership of complex digital IP through tape-out. Strong RTL and Verilog skills, synthesis and CDC tool experience, and knowledge of low-power design are expected.

  Verilog, UPF, CPF

  22d

  Summer 2027 Long Term ASIC Verification Engineering Intern/ Co-Op

  Ottawa, ON

  AI

  AMD, Inc.

  Candidates need to be 3rd or 4th year Computer Engineering or Computer Science students with digital design knowledge, object-oriented coding skills, and experience with SystemVerilog, C or C++. Python, Perl or other scripting experience and AI tools experience are assets, and valid work authorization is required.

  SystemVerilog, UVM, C, C++, Python, Perl

  23d

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

• 16d

  Senior ASIC Design Engineer - DSP/Analog/SerDes

  Ottawa, ON

  CC

  Celero Communications, Inc.

  10+ YOECandidates need a master's or PhD in electrical or computer engineering, 10+ years of digital ASIC design, and strong Verilog or SystemVerilog skills. Knowledge of DSP, high-speed SerDes, mixed-signal or optical communications is also required.

  Verilog, SystemVerilog, Python, Tcl, MATLAB, UVM

• 18d

  ASIC Verification Intern - Summer 2027

  Toronto, ON

  Full Time

  NC

  NVIDIA Canada Dev. Inc.

  Candidates need to be pursuing a BS or MS in Electrical or Computer Engineering. They need working knowledge of computer architecture, logic design, verification, algorithms and data structures, plus strong first-principles debugging and teamwork skills.

  Verilog, SystemVerilog, UVM, FPGA, Linux, Windows

• 21d

  Senior ASIC Verification Engineer

  Kanata, ON

  Full Time

  

  Myticas Consulting

  8+ YOECandidates need a related engineering degree, 8+ years of ASIC or SoC verification experience, and strong SystemVerilog, UVM and Python skills. Experience with SVA, functional coverage and formal verification tools is also needed.

  SystemVerilog, UVM, Python, Code coverage tools, Formal verification tools

• 22d

  Senior ASIC Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  2+ YOECandidates need a Bachelor's in electrical engineering (a Master's is preferred) and 2+ years supporting complex SoC silicon for server, storage or networking. They must have hands-on UVM, C/C++ and System Verilog experience, plus experience with third-party protocol VIPs such as PCIe, Ethernet and DDR.

  System Verilog, UVM, Perl, Python

  22d

  ASIC Physical Designer

  Ontario

  T

  Talentlab

  Candidates need experience with physical design CAD flows and design verification, and proficiency in DRC, LVS and debug methods. Hands-on Cadence Virtuoso, PERL or Shell scripting, and Unix/Linux skills are preferred, along with a bachelor's degree in a relevant field.

  Cadence Virtuoso, PERL, Shell, Unix/Linux

  22d

  Senior ASIC Verification Engineer

  Ottawa, ON

  Hybrid

  T

  Talentlab

  Candidates need an engineering degree, proven digital verification experience, and knowledge of formal verification and functional coverage. They should also be proficient in a programming language such as Python or C/C++ and be based in Ottawa.

  SystemVerilog, UVM, Python, C++, SystemC, Make

  22d

  Staff ASIC Design Engineer – AI/ML Hardware IP

  Toronto, ON

  T

  Talentlab

  5+ YOECandidates need at least 5 years of hands-on ASIC design experience and strong skills in Verilog, SystemVerilog, and logic synthesis. A degree in electrical or computer engineering is required, and candidates must be legally authorized to work on-site in Canada.

  Verilog, SystemVerilog, Design Compiler, PrimeTime, Formality, Spyglass

  22d

  Senior Staff ASIC Design Egineer - AI/ML Hardware IP

  Toronto, ON

  T

  Talentlab

  6+ YOECandidates need six or more years of ASIC design and integration experience (or a Master's plus five years, or a PhD plus four), strong Verilog/SystemVerilog skills, and experience owning complex SoC blocks. A Bachelor's, Master's or PhD in electrical engineering or a related field is required, and the candidate must be legally authorized to work in Canada.

  Verilog, SystemVerilog, VCS, Verdi, Questa, Xcelium

11 companies