“STA tools” jobs in Canada – Page 2

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• 27d

  Physical Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need hands-on ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and tape-out experience on advanced nodes such as 3nm, 5nm, 7nm or 16nm. A bachelor's or master's degree in computer or electrical engineering is required.

  Synopsys, Cadence, Mentor Graphics, Verilog

  27d

  STA/Constraints Engineer

  Vancouver, BC

  Full Time

  AI

  AMD, Inc.

  Candidates need industry experience in STA, constraints and timing signoff, and expert use of Synopsys PrimeTime and GCA (ICC2 or Fusion Compiler desired). Scripting in Perl, TCL, Shell or Python and Verilog RTL experience are valued.

  ICC2, Verilog

• 27d

  IC design Implementation and SignOff Architect, (STA SignOff)

  Canada

  Full Time

  C

  Cadence

  15+ YOECandidates need 15+ years of IC design implementation and signoff experience, deep advanced-node STA and ECO skills, and strong scripting in Tcl, Python or Perl. A BS or MS in electrical or computer engineering is required.

  Tempus, Certus, QRC

• 27d

  Senior Technical Analyst, Security Operations

  Victoria, BC

  

  Island Health

  5+ YOECandidates need a computer science diploma or degree and five years of recent experience administering security technologies such as malware detection, Cisco IPS and WSA, Tenable, Sentinel and LogRhythm SIEMs, and forensic tools. CISSP, SANS GIAC or forensics certification is strongly preferred.

  Sentinel, LogRhythm, Cisco Firepower, Cisco WSA, Tenable, forensics tools

• 28d

  Arborist

  West Vancouver, BC

  $37.40/hr

  

  Capilano Golf and Country Club

  3+ YOECandidates need a post-secondary credential in arboriculture, forestry or a related field and at least three years of relevant experience. ISA Certified Arborist is preferred, and equipment operation experience is an asset.

  Chainsaw, Chipper, Climbing equipment, Skid steer, Excavator, Tractor

• 1mo

  Associate Director, Vendor Management - Remote

  Burnaby, BC

  Full Time

  

  NTT DATA Canada, Inc.

  8+ YOECandidates need a bachelor's degree and 8 to 12 years of procurement, sourcing or vendor management experience, ideally in B2B indirect buying. Experience with SAP Ariba, ServiceNow, enterprise clients and hardware manufacturers such as Dell, HP and Lenovo is needed.

  SAP Ariba, ServiceNow

• 1mo

  Digital IC Designer

  Waterloo, ON

  Full Time

  

  onsemi: With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety,…

  5+ YOECandidates need a bachelor's degree in electrical or computer engineering or equivalent, and 5 to 10+ years of direct digital IC design experience with a track record of working products. Experience with CAD tools, scripting in Python or TCL, and DSP, microcontrollers or FPGA is an asset.

  VHDL, Python, TCL, FPGA, C

• 1mo

  Nurse Clinician, Skin & Wound Care - Medicine - Queen's Park Care Centre

  New Westminster, BC

  $49.20–$67.08/hr

  

  Fraser Health Authority

  3+ YOECandidates need current BCCNM registration as a Registered Nurse, three years of recent skin and wound care experience including one year of education or leadership, and post-graduate wound care certification such as IIWCC, CAET or WOCN. A valid BC driver's licence and a personal vehicle for business use are also required.

  Wound care, Leadership, RN, Teaching, Work independently, Research

• 1mo

  ASIC Physical Design, Sr Staff Engineer - 16724

  Nepean, ON

  S

  Synopsys

  9+ YOECandidates need 9+ years of ASIC physical design experience on complex SoC or test chip projects at advanced nodes. They must know the full physical design flow and tools such as Design Compiler, PrimeTime, IC Compiler II, Calibre and RedHawk, and must be authorized to work in the USA.

  Design Compiler, PrimeTime, IC Compiler II, ICV, Calibre, RedHawk

• 1mo

  Senior Trust Advisor

  Vancouver, BC +1

  $110k–$135k/yrFull Time

  

  Raymond James Ltd.

  3+ YOECandidates need at least 3 years of estate, trust or financial planning experience, with preference for managing estate, trust and power of attorney accounts. A university degree, strong communication and analytical skills, and experience with high-net-worth clients are required, and STEP or MTI designation is an asset.

  Sales, Presentation skills, Collaboration, Regulatory compliance, Risk management, Compensation and benefits

• 1mo

  Sr. Manager, Physical Design Engineering, Annapurna Labs

  Toronto, ON

  Full Time

  AD

  Amazon Development Centre Canada ULC

  10+ YOE5+ MgmtAmazon Development Centre Canada needs 5+ years leading physical design teams of 8+ engineers and 10+ years of hands-on ASIC/SoC physical design across advanced nodes. Candidates must master both Synopsys and Cadence EDA tools, advanced STA and power integrity, and hierarchical flows for very large SoCs.

  Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC, RedHawk-SC, Cadence Innovus

• 1mo

  Physical Design Engineer

  Vancouver, BC

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in computer or electrical engineering and hands-on ASIC physical design experience from RTL to GDSII. Strong Verilog, timing analysis, low-voltage design and advanced-node tape-out experience (3nm to 16nm) are preferred.

  Synopsys tools, Cadence tools, Mentor Graphics tools, Verilog

  1mo

  SoC Design Lead, Microarchitecture and Design Methodology

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a strong foundation in computer architecture and digital design, with knowledge of static timing analysis, clocks and power optimization. Verilog or SystemVerilog experience, with UVM preferred, and strong communication and teamwork skills are needed.

  Verilog, SystemVerilog, UVM

  1mo

  Silicon Design Engineer - Technical Lead

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Advanced Micro Devices needs candidates with experience in I/O protocols such as USB, PCIe and CXL, plus micro-architecture and RTL design for high-speed, low-power digital blocks. A master's or bachelor's degree in electrical engineering or equivalent is preferred.

  Python, Perl

  1mo

  Physical Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  8+ YOECandidates need a bachelor's, master's or PhD in electrical, electronics or computer engineering, with 8, 4 or 2 years of physical design experience respectively. They need expertise in block-level place and route, timing closure, physical verification and power, performance and area optimization, plus hands-on debugging of EDA tools from Synopsys, Cadence and Siemens.

  Synopsys ICC2, Cadence Innovus, Synopsys PrimeTime, Spyglass, RedHawk, Calibre

  1mo

  RTL Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need experience with I/O protocols such as USB, PCIe and CXL, plus RTL design for multi-clock, high-frequency, low-power designs. Strong analytical, communication and teamwork skills are expected, along with scripting in Python or Perl.

  RTL, DFT, Firmware, Analytical skills, Problem solving, Attention to detail

  1mo

  Physical Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates at Advanced Micro Devices need ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and hands-on tape-out experience on 3nm to 16nm SoCs. They also need experience with Synopsys, Cadence or Mentor Graphics CAD tools and a bachelor's or master's degree in electrical or computer engineering.

  Synopsys tools, Cadence tools, Mentor Graphics tools, Verilog

  1mo

  SoC Lead Engineer – LEC & Low Power Signoff

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Advanced Micro Devices needs candidates with proven SoC implementation and tapeout experience, deep knowledge of equivalence checking and low power verification, and hands-on use of industry EDA tools. Strong scripting, debugging, leadership and communication skills are also required, along with a BS or MS in Electrical Engineering, ECE, EEE or a related field.

  Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler

  1mo

  STA/Constraints Engineer

  Vancouver, BC

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need industry experience in static timing analysis, constraints and timing signoff, plus expert use of Synopsys PrimeTime and GCA. Scripting in Perl, TCL, Shell or Python, and a degree in microelectronics or a related field, are preferred.

  GCA, ICC2, Verilog, Perl, TCL, Python

  1mo

  SoC Physical Design Implementation Lead

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Advanced Micro Devices needs candidates with deep hands-on experience in place and route, static timing analysis and clock distribution on large SoCs. Strong skills in advanced process nodes, power optimization, CAD tools from Synopsys, Cadence and Siemens, and scripting in Tcl, Perl or Shell are expected. A Bachelor's or Master's in electrical or computer engineering is preferred.

  Synopsys tools, Cadence tools, Siemens (Mentor Graphics) tools, Tcl, Perl, Shell

• 1mo

  SOC Development Engineer

  Vancouver, BC

  $134k–$201k/yrOn-siteFull Time

  

  Solidigm: Solidigm is a leading global provider of innovative NAND flash memory solutions.

  10+ YOECandidates need a bachelor's degree in electrical or computer engineering or computer science, strong debugging skills, digital logic design experience in advanced technology nodes, and verification experience with UVM or FPV. Preferred candidates have 10+ years of ASIC/SoC experience and familiarity with NVMe, PCIe, DDR or ARM standards.

  Verilog, VHDL, SystemVerilog, UVM, Jira, Confluence

• 1mo

  High Level Synthesis Compiler Engineer

  Toronto, ON

  Full Time

  AS

  Altera Semiconductor Technology Canada ULC

  8+ YOECandidates need a Bachelor's or Master's degree in an engineering or computer science field and 8+ years building compilers, LLVM/MLIR tools or EDA/FPGA software. They must know production C++, MLIR or LLVM, FPGA design and implementation flows, and be able to mentor engineers and work with customers.

  C++, LLVM, MLIR

• 1mo

  Static Timing Analysis (STA) Engineer

  Toronto, ON

  Full Time

  A

  Altera

  6+ YOECandidates need 6+ years of static timing analysis experience on ASIC or FPGA designs, plus a strong grasp of STA fundamentals and tools such as PrimeTime. A bachelor's or master's degree in electrical or computer engineering, with RTL design knowledge, is required.

  PrimeTime, Verilog, SystemVerilog, Tcl, Python

  1mo

  FPGA Compiler (Placer) Engineer

  Toronto, ON

  Full Time

  A

  Altera

  6+ YOECandidates need 6+ years in FPGA or ASIC CAD, EDA tools or physical design, strong algorithms skills, and C/C++ experience. A bachelor's or master's in electrical, computer engineering or computer science is required.

  Quartus, Vivado, C++, Python, Tcl

14 companies