“UVM” jobs in Canada – Page 2

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• 13d

  Sr Manager or Principal Engineer for Firmware Development - 19315

  Markham, ON

  S

  Synopsys

  10+ YOECandidates need a Bachelor's, Master's or PhD in computer or electrical engineering, or equivalent experience, with 10+ years in a related field. They need strong skills in digital logic and firmware development, proficiency in C, Verilog and SystemVerilog/UVM, and experience leading complex projects.

  Verilog, UVM, C, Python, Perl, Bash

  27d

  Staff Application Engineer

  Mississauga, ON

  S

  Synopsys

  7+ YOECandidates need a bachelor's degree in electrical and electronics engineering with 7+ years of applications, verification or emulation experience, or a master's with 5+ years. They need hands-on emulation platform experience, HDL and UVM skills, and scripting in Python, Perl or TCL.

  Synopsys ZeBu, Mentor Veloce, Cadence Palladium, Verilog, SystemVerilog, VHDL

• 14d

  Engineering Student - FPGA Verification - Winter 2027

  Sainte-Anne-de-Bellevue, QC

  Full Time

  

  MDA

  Candidates need completion of a third year of an electrical or computer engineering bachelor's degree with a 3.2/4.0 minimum GPA. They need a desire to learn, initiative, and a collaborative attitude, plus security clearance eligibility.

  SystemVerilog, VHDL, Verilog, Tcl, Python, C/C++

• 20d

  Senior Verification Engineer – High Speed Coherent Interconnect Hub

  Toronto, ON

  Full Time

  NC

  NVIDIA Canada Dev. Inc.

  3+ YOECandidates need a BS or MS or equivalent experience, plus 3+ years of ASIC verification work on complex IP or SoC subsystems. Strong skills in SystemVerilog, UVM and coverage-driven verification are required.

  SystemVerilog, UVM, Python, Perl, Shell

  24d

  ASIC Verification Intern - Summer 2027

  Toronto, ON

  Full Time

  NC

  NVIDIA Canada Dev. Inc.

  Candidates need to be pursuing a BS or MS in Electrical or Computer Engineering. They need working knowledge of computer architecture, logic design, verification, algorithms and data structures, plus strong first-principles debugging and teamwork skills.

  Verilog, SystemVerilog, UVM, FPGA, Linux, Windows

• 20d

  ASIC Verification Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in computer or electrical engineering, plus interest in ASIC verification and digital design. Experience with SystemVerilog, C or C++, and scripting languages such as Python or Perl is an asset.

  SystemVerilog, UVM, Claude Code, Codex, Python, Perl

  27d

  GPU Design Verification Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need experience with IP-level ASIC verification, UVM testbenches, Verilog and SystemVerilog, and scripting in Python or Perl. Advanced Micro Devices prefers a Bachelor's or Master's in computer or electrical engineering.

  Verilog, UVM, C/C++, Perl, Python, Makefile

• 20d

  ASIC Verification Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a bachelor's or master's in computer or electrical engineering and an understanding of digital design. Experience with SystemVerilog, C or C++, and scripting such as Python or Perl is preferred.

  SystemVerilog, UVM, Claude Code, Codex, Python, Perl

  27d

  GPU Design Verification Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need IP-level ASIC verification experience, UVM testbench skills, and knowledge of SystemVerilog, Verilog, C/C++ and scripting in Python, Perl or shell. A Bachelor's or Master's in computer or electrical engineering is preferred.

  UVM, Verilog, C++, Python, Perl, Makefile

  28d

  Summer 2027 Long Term ASIC Verification Engineering Intern/ Co-Op

  Ottawa, ON

  AI

  AMD, Inc.

  Candidates need to be 3rd or 4th year Computer Engineering or Computer Science students with digital design knowledge, object-oriented coding skills, and experience with SystemVerilog, C or C++. Python, Perl or other scripting experience and AI tools experience are assets, and valid work authorization is required.

  SystemVerilog, UVM, C, C++, Python, Perl

• 22d

  Senior Digital ASIC Design Engineer - DSP/Analog/SerDes

  Ottawa, ON

  CC

  Celero Communications, Inc.

  10+ YOECandidates need a Master's or PhD in electrical or computer engineering, 10+ years of digital ASIC design, and strong Verilog or SystemVerilog skills. Knowledge of DSP, high-speed SerDes, mixed-signal or optical communications, plus ASIC flows and EDA tools, is also required.

  Verilog, SystemVerilog, Python, Tcl, MATLAB, UVM

• 24d

  Sr FPGA Programmer - Test et Vérification DO-254

  Montréal, QC

  Full Time

  

  Thales

  10+ YOEDiplôme d'ingénieur ou Master 2 / Doctorat, 5 à 10 ans d'expérience en vérification; Maîtrise de VHDL et UVM; Expérience avec Questa ou ModelSim et outils Aldec

  Questa, ModelSim, Aldec Active-HDL, Git, DOORS, Polarion

• 24d

  Sr FPGA Programmer - Test et Vérification DO-254

  Montréal, QC

  HybridFull Time

  TC

  Thales Canada Inc., Avionics

  10+ YOEDiplôme d'ingénieur ou Bac+5 avec 5 à 10 ans d'expérience en vérification; Maîtrise de VHDL et UVM, simulation avec Questa ou ModelSim; Connaissance approfondie de DO-254 et des métriques de code coverage

  Questa, ModelSim, Aldec Active-HDL, Git, DOORS, Polarion

  24d

  Sr FPGA Programmer - Test et Vérification DO-254

  Montréal, QC

  HybridFull Time

  TC

  Thales Canada Inc., Avionics

  10+ YOEDiplôme d'ingénieur ou Bac+5 avec 5 à 10 ans d'expérience en vérification; Maîtrise de VHDL et UVM, simulation avec Questa ou ModelSim; Connaissance approfondie de DO-254 et des métriques de code coverage

  Questa, ModelSim, Aldec Active-HDL, Git, DOORS, Polarion

• 25d

  RTL Design Engineer - AI Tools

  Toronto, ON

  $100–$175/hr

  

  Mercor

  3+ YOECandidates need 3 to 10 years of digital RTL design or design verification experience, strong Verilog, SystemVerilog and UVM skills, and solid digital design fundamentals. Experience with ASIC design flows and EDA tools is also required.

  Verilog, SystemVerilog, UVM, EDA tools

  25d

  Design Verification Engineer - Fully Remote | Upto $175/hr

  Toronto, ON

  $100–$175/hr

  

  Mercor

  3+ YOECandidates need 3 to 10 years of digital RTL design or design verification experience, strong Verilog/SystemVerilog and UVM skills, and solid knowledge of digital design fundamentals. They also need ASIC design flow experience and the ability to write clear design documentation.

  Verilog, SystemVerilog, UVM, EDA tools

• 27d

  FPGA Design & Validation Engineer – 4G/5G Radio

  Ottawa, ON

  Contract

  

  Myticas Consulting

  7+ YOECandidates need proven FPGA and RTL design experience, expertise in NR, LTE, eCPRI, CPRI and PTP protocols, and knowledge of the O-RAN ecosystem. Experience with UVM, Git and tools like Quartus, Vivado and MATLAB/Simulink is also required.

  Quartus, Vivado, MATLAB/Simulink, HDL Coder, Git, GitHub

  27d

  Senior ASIC Verification Engineer

  Kanata, ON

  Full Time

  

  Myticas Consulting

  8+ YOECandidates need a related engineering degree, 8+ years of ASIC or SoC verification experience, and strong SystemVerilog, UVM and Python skills. Experience with SVA, functional coverage and formal verification tools is also needed.

  SystemVerilog, UVM, Python, Code coverage tools, Formal verification tools

  27d

  FPGA Developer / FPGA Design Engineer (4G/5G Radio – Datapath / RU FPGA Design)

  Ottawa, ON

  Contract

  

  Myticas Consulting

  1+ YOECandidates need strong FPGA and DSP fundamentals, SystemVerilog and MATLAB/Simulink experience, and knowledge of AXI and Ethernet. Radio protocol knowledge such as O-RAN, eCPRI and PTP is desirable, and 1 to 5 years of experience is encouraged.

  Altera Quartus, MATLAB, Simulink, SystemVerilog

• 28d

  Co-op ASIC Digital Verification Engineer

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  Candidates need good academic standing, object-oriented coding skills and strong problem-solving ability. Knowledge of Verilog, SystemVerilog, UVM, Python or Tcl is an asset, and English proficiency is required.

  Verilog, SystemVerilog, UVM, Python, Tcl

  28d

  ASIC Digital Verification Engineer

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  Candidates need knowledge of chip specifications and verification plans, plus SystemVerilog and UVM for digital verification. Experience with Synopsys or Cadence simulators, SystemVerilog assertions, functional and code coverage, and working in Unix/Linux is also needed.

  SystemVerilog, UVM, Unix, Linux

• 28d

  Senior ASIC Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  2+ YOECandidates need a Bachelor's in electrical engineering (a Master's is preferred) and 2+ years supporting complex SoC silicon for server, storage or networking. They must have hands-on UVM, C/C++ and System Verilog experience, plus experience with third-party protocol VIPs such as PCIe, Ethernet and DDR.

  System Verilog, UVM, Perl, Python

  28d

  Staff Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  9+ YOECandidates need a Bachelor's or Master's in computer science, electrical engineering or a related field, plus at least 9 years of ASIC design verification experience. Strong SystemVerilog and UVM skills and advanced debugging are required.

  SystemVerilog, UVM, EDA tools

  28d

  Senior Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  3+ YOETalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.

  SystemVerilog, UVM, Python, Perl, C/C++, GNU Make

12 companies