ASIC Physical Design, Sr Staff Engineer - 16724
Nepean, ONSynopsys
9+ YOECandidates need 9+ years of ASIC physical design experience on complex SoC or test chip projects at advanced nodes. They must know the full physical design flow and tools such as Design Compiler, PrimeTime, IC Compiler II, Calibre and RedHawk, and must be authorized to work in the USA.
Design Compiler, PrimeTime, IC Compiler II, ICV, Calibre, RedHawk
Analog Design, Sr Staff Engineer - 18144
Kanata, ONSynopsys
8+ YOECandidates need a master's degree with 8+ years or a PhD with 6+ years of analog circuit design experience. Experience with op-amps, current mirrors and bandgaps is required, and SERDES or DDR knowledge is strongly desired.
CAD tools for analog design
Analog Design, Principal Engineer- 18339
Markham, ONSynopsys
8+ YOECandidates need 8+ years of CMOS analog or mixed-signal design experience and strong expertise in transistor-level and SerDes circuits. Hands-on FinFET layout, SPICE and scripting skills, and knowledge of reliability and ESD design are also required.
SPICE simulators, EDA tools, Python, TCL
Principal Physical Design Methodology Engineer
Markham, ONSynopsys
10+ YOECandidates need a Bachelor's or Master's in Electrical or Computer Engineering and 10+ years of ASIC digital implementation experience. Deep expertise with Fusion Compiler or ICC2, high-speed IP experience, and Tcl and Python scripting are required.
Fusion Compiler, ICC2, Innovus, PrimeTime, PrimePower, Tcl
Analog Design, Manager - 18463
Kanata, ONSynopsys
8+ YOE2+ MgmtCandidates need an M.A.Sc. with 8+ years or a PhD with 6+ years of analog or mixed-signal IC design experience, plus 2+ years of people management. They must have deep Multi-Gbps SerDes expertise, transistor-level design skills, and experience with SPICE, Verilog-A and layout.
SPICE, Verilog-A, Industry-standard simulation tools
Silicon Validation Engineer
Mississauga, ONSynopsys
6+ YOECandidates need a Master's in electrical or electronics engineering with 6+ years of post-silicon validation experience, or a Bachelor's with 7+ years. Hands-on lab skill with BERTs, oscilloscopes, VNAs and TDRs, plus MATLAB and Python, is required.
BERT, real-time oscilloscope, sampling oscilloscope, VNA, TDR, MATLAB
Analog Design, Sr Staff Engineer - 18597
Ottawa, ONSynopsys
7+ YOECandidates need an engineering or applied science degree and 7 to 12 years of semiconductor, Silicon IP or SoC experience. Strong project management, customer communication and cross-functional leadership skills are required, along with familiarity with Linux environments.
Linux
Project Engineering Management, Principal Engineer
Mississauga, ONSynopsys
10+ YOECandidates need an engineering degree or equivalent experience, 10+ years of customer-facing project management, and familiarity with mixed-signal IP, SoC or ASIC development. Strong communication, MS Project, Jira, UNIX/Linux and quality management system knowledge are also required.
MS Project, Jira, UNIX, Linux
ASIC Digital Verification, Sr. Manager
Mississauga, ONSynopsys
15+ YOECandidates need a BS or MS in EE, EC or VLSI with 15+ years of IP or SoC verification experience, and strong team leadership. They must know Verilog, SystemVerilog and UVM, and Perl or Python automation. PCIe and Ethernet knowledge is an asset.
Verilog, SystemVerilog, UVM, Perl, Python