Senior ASIC Design Engineer - Client IP
Ottawa, ON$112k–$179k/yrFull Time
CC
Ciena Canada ULC
5+ YOECandidates need an engineering degree at the bachelor or master level and 5+ years of SystemVerilog design and digital synthesis, timing closure and clock-crossing experience. Strong independent problem solving, English communication, and knowledge of verification and timing/power/area trade-offs are required.
Git, Jira, Python, Make, bash