“RTL simulation tools” jobs in Canada – Page 4

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• 29d

  Senior Firmware Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need extensive embedded firmware experience with microcontrollers and C or assembly, plus a bachelor's or master's degree in an engineering or applied science field. Experience with RTOS, Python, Git, Agile and pre-silicon environments is preferred.

  Git, GitHub Actions

• 29d

  Design Verification Engineer — Memory Subsystem (Vancouver)

  Vancouver, BC

  On-site

  QC

  Qualcomm Canada ULC

  3+ YOECandidates need a bachelor's or master's degree in an engineering or computer science field and 3 to 10 years of chip or subsystem verification experience. Hands-on skill with Verilog, SystemVerilog, UVM and assertions is required, and knowledge of memory standards such as DDR, LPDDR and HBM is preferred.

  Verilog, SystemVerilog, UVM, SystemVerilog Assertions, waveform viewers

  29d

  FY27 Intern - Compute DSP/AI Processor Engineering Internship - Canada (16 months)

  Markham, ON

  On-siteInternship

  QC

  Qualcomm Canada ULC

  1+ YOECandidates need to be enrolled toward a bachelor's degree in engineering or computer science, available May or June 2027 to August or September 2028, and have digital design knowledge with Verilog or VHDL. Strong problem-solving, communication and teamwork skills are also required.

  SystemVerilog, Verilog, VHDL, UVM, SystemC, Python

• 29d

  Senior Hardware Engineer

  Burnaby, BC

  $108k–$153k/yrFull Time

  

  LMI Technologies

  5+ YOECandidates need a bachelor's degree in electrical engineering and at least five years designing and testing digital logic such as FPGAs or ASICs. Hands-on experience with VHDL or Verilog, high-speed interfaces and self-verifying simulation environments is required.

  Vivado, Chipscope, Logic analyzers, Oscilloscopes, Xilinx IP, Intel FPGA

• 29d

  FPGA Engineer

  Ottawa, ON

  $105k–$145k/yrFull Time

  

  Q-Block Computing: Imagine instruments precise enough to probe this reality—to ask whether the cosmos operates according to Nature’s own algorithms.

  4+ YOECandidates need a related engineering degree, 4+ years of professional FPGA design and verification experience, and hands-on work with Vivado, Quartus or Lattice toolchains. They also need strong high-speed digital design skills and proficiency with oscilloscopes, logic analyzers and signal generators.

  Xilinx Vivado, Intel Quartus, Lattice toolchain, oscilloscope, logic analyzer, signal generator

• 29d

  SMTS Logic Design

  Montréal, QC

  

  Rambus: As an industry pioneer with over 30 years experience, Rambus is a premier provider of chips & silicon IP.

  8+ YOECandidates need a BS, MS or PhD in electrical or computer engineering, 8+ years of ASIC/SoC logic design experience, and expert SystemVerilog skills. Experience with synthesis, timing closure and PCIe Gen5/Gen6/Gen7 is preferred.

  SystemVerilog, Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, SpyGlass, Questa

• 29d

  FPGA Designer

  Newfoundland and Labrador

  

  Avalon Holographics Incorporated

  5+ YOECandidates need a Bachelor's in Electrical Engineering or a related field and 5+ years of RTL design in VHDL or Verilog. Experience with FPGA tools, DSP or video pipelines, and verification strategies is required.

  VHDL, Verilog

• 29d

  Senior/Expert Hardware Design Engineer - FPGA

  Montréal, QC

  On-siteFull Time

  

  Sopra Steria: The Group provides end-to-end solutions to make large companies and organisations more competitive by combining in-depth knowledge of a wide range…

  5+ YOECandidates need a bachelor's or master's degree in electrical or electronic engineering and at least 5 years of FPGA design experience with Xilinx devices or airborne electronic hardware. They also need Vivado, VHDL or Verilog, video pipeline experience, and fluency in French and English.

  Vivado, VHDL, Verilog, SystemVerilog, DisplayPort, HDMI

• 29d

  System Architect Verification Engineer

  Ottawa, ON

  On-siteFull Time

  R

  Ranovus

  6+ YOECandidates need a Bachelor's in Electrical Engineering or related field with 6+ years, or a PhD with 3+ years, in digital or mixed-signal verification using SystemVerilog. Familiarity with RTL simulation tools, closed-loop control, photonic components and Python or MATLAB is also required.

  SystemVerilog, Verilog-A, Verilog-AMS, SPICE, Python, MATLAB

• 1mo

  Data Center Silicon Hardware Engineering Intern - BS - 2027 Co-Op

  Ottawa, ON +1

  Full Time

  MM

  MSI - (Marvell Semiconductor Inc.) US

  Candidates need to be enrolled full-time in a BS in electrical or computer engineering, with coursework in digital circuits and computer architecture. Experience with Verilog or SystemVerilog and C, C++ or Python is needed, and prior hardware projects are an asset.

  Verilog, SystemVerilog, UVM

  1mo

  Data Center Silicon Hardware Engineering Intern - BS - 2027 Co-Op

  Ottawa, ON +1

  Full Time

  MM

  MSI - (Marvell Semiconductor Inc.) US

  Candidates need to be full-time BS students in electrical engineering, computer engineering, or a related field. They need coursework in digital logic and computer architecture, plus experience with C, C++, Python, Verilog, or SystemVerilog.

  Verilog, SystemVerilog, UVM

• 1mo

  High Level Synthesis Compiler Engineer

  Toronto, ON

  Full Time

  AS

  Altera Semiconductor Technology Canada ULC

  8+ YOECandidates need a Bachelor's or Master's degree in an engineering or computer science field and 8+ years building compilers, LLVM/MLIR tools or EDA/FPGA software. They must know production C++, MLIR or LLVM, FPGA design and implementation flows, and be able to mentor engineers and work with customers.

  C++, LLVM, MLIR

  1mo

  IP Firmware Design Engineer

  Toronto, ON

  Full Time

  AS

  Altera Semiconductor Technology Canada ULC

  2+ YOECandidates need a bachelor's degree in an engineering or computer science field, 2+ years of digital hardware design or verification (SystemVerilog, Verilog or VHDL), and 2+ years of scripting or software programming (Python, TCL, Perl, C or C++).

  Quartus Prime, SystemVerilog, Verilog, VHDL, Python, TCL

• 1mo

  Senior SoC Design Engineer

  Burnaby, BC

  $86k–$186k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  3+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering and 3 to 5 years of related experience, including RTL design in SystemVerilog and Verilog. Experience with ASIC design flows, synthesis, static timing analysis and PCI-Express is valued.

  Synopsys Design Compiler, Cadence Incisive, Verilog, Perl, Python, Tcl

• 1mo

  ASIC Front End Implementation Engineer

  Ottawa, ON

  Full Time

  CC

  Ciena Canada ULC

  5+ YOECandidates need a B.Sc. in electrical or computer engineering and 5+ years of ASIC digital design and DFT experience. They must have hands-on DFT and synthesis tool skills and be able to work well in engineering teams.

  Synthesis tools, Static timing analysis tools, DFT tools, EDA tools

• 1mo

  Field Application Engineer - AMD/Xilinx

  Pointe-Claire, QC

  Full Time

  AC

  Avnet Canada

  8+ YOECandidates need systems-level experience with FPGA and ASIC design tools, especially Vivado/Vitis, ISE or Quartus. They also need strong communication and problem-solving skills and typically 8+ years of experience with a bachelor's degree or equivalent.

  Vivado, Vitis, ISE, Quartus, ModelSim, IP Integrator

• 1mo

  DV - Staff Verification Engineer - Serdes

  Canada

  On-siteFull Time

  E

  Eliyan

  7+ YOECandidates need at least 7 years of verification experience, including 4 years in PHY or high-speed interfaces, with deep SerDes/PCIe PHY expertise and strong UVM/SystemVerilog skills. Eliyan also values experience verifying mixed-signal IP and integrating VIPs.

  SystemVerilog, UVM, Jasper Gold, vc-formal, Python, Perl

• 1mo

  Staff Design Verification Engineer, AI HW

  Toronto, ON

  

  Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.

  Candidates need experience with modern verification methods and strong SystemVerilog skills, plus Linux scripting in Python or Bash. They should be comfortable with coverage-driven verification and debugging across RTL, testbenches and workloads.

  SystemVerilog, Python, Bash, Linux

• 1mo

  CPU Performance Modeling (Lead & ICs)

  Canada

  HybridFull Time

  

  NUVACORE

  8+ YOECandidates need an MS in computer architecture or a related field and deep expertise in CPU performance modelling. They must have years of C++ simulator work, strong C++ and Python or Perl skills, and proven results from pathfinding through silicon.

  gem5, C++, Python, Perl

  1mo

  CPU Micro-Architect / RTL (Lead & IC Engineers)

  Canada

  HybridFull Time

  

  NUVACORE

  7+ YOECandidates need a BS or MS with 15+ years of CPU design experience for leads or 7+ years for individual contributors. They must know Verilog, simulation and logic and physical design, and understand RISC-V, ARM64 or x86 ISAs.

  Verilog, AI tools for RTL coding, simulation tools, emulation

• 1mo

  Senior FPGA Designer

  Montréal, QC

  HybridFull Time

  E

  Exegy

  5+ YOEDiplôme en génie électronique, électrique ou informatique; Cinq ans ou plus d'expérience en conception FPGA; Maîtrise avancée du VHDL et/ou du Verilog

  Vivado, Git, Jenkins, Python, Linux

• 1mo

  Hardware Intern - AI HW & SoC (Canada)

  Ottawa, ON +1

  

  Tenstorrent University Jobs: Tenstorrent is a next-generation computing company that builds computers for AI.

  Candidates need to be students in EE, ECE, CE or CS with coursework in digital design and computer architecture. They should know ASIC concepts such as RTL, verification, logic synthesis and timing analysis, and have scripting or programming skills.

  Python, C++, PERL, tcl, architectural simulator

• 1mo

  Sr. Principal Program Manager, ASIC Design

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  10+ YOEAstera Labs needs a candidate with 10+ years in ASIC or SoC development, including 3+ years in technical program management. Candidates need hands-on knowledge of the chip design flow, EDA and CAD tools, and pre-silicon validation.

  CAD infrastructure, Emulation platforms, FPGA prototyping platforms

  1mo

  Senior Digital Design Engineer

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  2+ YOECandidates need a bachelor's degree in electrical or electronics engineering, 2 to 5 years of digital design experience on complex chips, and hands-on SystemVerilog or Verilog RTL skills. PCIe or Ethernet IP experience and Python or Perl scripting are also required, and candidates must be authorized to work in Canada.

  SystemVerilog, Verilog, Synopsys, Cadence, Python, Perl

19 companies