“UVM” jobs in Canada – Page 3

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• 1mo

  Staff Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  9+ YOECandidates need a Bachelor's or Master's in computer science, electrical engineering or a related field, plus at least 9 years of ASIC design verification experience. Strong SystemVerilog and UVM skills and advanced debugging are required.

  SystemVerilog, UVM, EDA tools

  1mo

  Senior Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  3+ YOETalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.

  SystemVerilog, UVM, Python, Perl, C/C++, GNU Make

  1mo

  Senior ASIC Verification Engineer

  Ottawa, ON

  Hybrid

  T

  Talentlab

  Candidates need an engineering degree, proven digital verification experience, and knowledge of formal verification and functional coverage. They should also be proficient in a programming language such as Python or C/C++ and be based in Ottawa.

  SystemVerilog, UVM, Python, C++, SystemC, Make

• 1mo

  Design Verification Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  AMD asks for advanced ASIC functional verification experience and hands-on work on multiple projects or tapeouts. Candidates need Verilog, SystemVerilog, UVM, scripting skills, and a Bachelor's or Master's in Computer or Electrical Engineering.

  Verilog, UVM, Makefiles, Perl, Python, Ruby

  1mo

  Silicon Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a bachelor's degree in electrical or computer engineering, with a master's or PhD preferred. AMD wants hands-on ASIC firmware and hardware verification experience with UVM, SystemVerilog, C/C++ and bus protocols such as AXI and AHB.

  UVM, Verilog, C-DPI, Python, Perl, Make

  1mo

  Verification Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need strong SystemVerilog and UVM skills, experience with ASIC or SoC verification, and familiarity with constrained-random, coverage-driven and formal verification. A Bachelor's or Master's in computer or electrical engineering is required.

  UVM, Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal

  1mo

  SoC Design Lead, Microarchitecture and Design Methodology

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a strong foundation in computer architecture and digital design, along with static timing analysis, clock and power optimization knowledge. Experience with Verilog or SystemVerilog, and UVM preferred, plus strong communication and teamwork skills.

  Verilog, SystemVerilog, UVM

  1mo

  Silicon Design Verification Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a Bachelor's or Master's in Computer or Electrical Engineering, knowledge of digital design and computer architecture, and hands-on SystemVerilog, UVM and C++ or Python experience. Prior verification work and PCIe or AXI protocol knowledge are assets.

  UVM, C++, Python, Formal verification tools

  1mo

  Design Verification Lead

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a bachelor's or master's degree in electrical or computer engineering, computer science or a related field, plus UVM and SystemVerilog experience and knowledge of high-speed protocols such as PCIe, CXL or Ethernet. Scripting in Python or Perl and technical leadership skills are also needed.

  SystemVerilog, Verilog, UVM, Python, Perl

• 1mo

  Design Verification Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer engineering or computer science. They need coding skills in SystemVerilog, C/C++ or Python, Linux and Git familiarity, and strong debugging ability.

  VCS, Verdi, DVE

• 1mo

  Design Verification Lead

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong UVM and SystemVerilog skills, and experience verifying high-speed protocols such as PCIe, CXL or Ethernet. Technical leadership, mentoring and scripting in Python or Perl are preferred.

  SystemVerilog, Verilog, UVM, Python, Perl

  1mo

  Design Verification Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need hands-on hardware verification experience across multiple projects or tapeouts, with SystemVerilog, UVM, Verilog and scripting skills. A Bachelor's or Master's in Computer or Electrical Engineering is expected.

  UVM, Verilog, Makefiles, Perl, Python, Ruby

  1mo

  Verification Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need strong SystemVerilog and UVM skills, solid ASIC/SoC verification experience, and familiarity with constrained-random, coverage-driven and formal (SVA) methods. A bachelor's or master's in computer or electrical engineering is required.

  Synopsys VCS, Cadence IES, Cadence IEV, Jasper, VC-Formal, Magellan

  1mo

  Silicon Design Verification Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's in Computer or Electrical Engineering, plus knowledge of digital logic and computer architecture. Experience with SystemVerilog, UVM, C++ and Python, and protocols such as PCIe or AXI, is preferred.

  UVM, C++, Python, SVA formal tools

  1mo

  SoC Design Lead, Microarchitecture and Design Methodology

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  AMD needs candidates with a strong foundation in digital design, computer architecture, static timing analysis and power optimization. Strong written and verbal communication, analytical skills and a degree in computer, electrical engineering or a related field are preferred.

  Verilog, SystemVerilog, UVM

  1mo

  Silicon Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's degree in electrical or computer engineering, with a master's or PhD preferred. Experience with ASIC hardware and firmware design and verification, C/C++ and SystemVerilog, and bus protocols like AXI and AHB is preferred.

  UVM, C-DPI, Verilog, FPGA prototyping platforms, Python, Perl

• 1mo

  Principal Digital Verification Engineer

  Nepean, ON

  S

  Synopsys

  12+ YOESynopsys candidates need 12+ years of verification experience with a BSc, 10+ years with an MSc, or 8+ years with a PhD. They need deep SystemVerilog and UVM skills, simulation and waveform debugging, C knowledge, assertion-based verification, and Linux scripting. Experience with LPDDR5/5X or LPDDR6 and emulation platforms is a plus.

  SystemVerilog, UVM, waveform debugger, Linux, source control, emulation platform

  1mo

  ASIC Digital Design, Principal Engineer-18731

  Mississauga, ON

  S

  Synopsys

  Candidates need extensive mixed-signal ASIC or IP verification experience, strong PCIe and PCIe PHY knowledge, and hands-on SystemVerilog and UVM skills. Strong debugging and mentoring abilities are also required.

  SystemVerilog, UVM

  1mo

  ASIC Digital Verification, Sr. Manager

  Mississauga, ON

  S

  Synopsys

  15+ YOECandidates need a BS or MS in EE, EC or VLSI with 15+ years of IP or SoC verification experience, and strong team leadership. They must know Verilog, SystemVerilog and UVM, and Perl or Python automation. PCIe and Ethernet knowledge is an asset.

  Verilog, SystemVerilog, UVM, Perl, Python

• 1mo

  Staff ASIC Verification Engineer, Low Power AI

  Markham, ON

  On-site

  

  Qualcomm Canada ULC

  4+ YOEQualcomm Canada ULC needs candidates with a relevant degree and 4+ years of ASIC work (3+ with a master's, 2+ with a PhD). Expert knowledge of Verilog, VHDL and SystemVerilog UVM is required, plus solid C skills.

  SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl

  1mo

  Digital Design Verification Engineer, Staff

  Toronto, ON

  On-site

  

  Qualcomm Canada ULC

  4+ YOECandidates need a bachelor's degree in a science or engineering field with 4+ years of ASIC design or verification experience, or an equivalent master's or PhD with less experience. Strong SystemVerilog, UVM and scripting skills and proven leadership and communication are required.

  Verilog, SystemVerilog, UVM, Python, Perl, C/C++

• 1mo

  Design Verification Engineer, Annapurna Labs

  Toronto, ON

  Full Time

  AD

  Amazon Development Centre Canada ULC

  4+ YOECandidates need a bachelor's degree in electrical engineering or a related field and at least 4 years of design verification experience using constrained-random simulation such as UVM. Strong debugging skills across IP, SoC and full-system levels are required.

  UVM, Python, Perl, C++

  1mo

  Design Verification Engineer - technical lead, Annapurna Labs

  Toronto, ON

  Full Time

  AD

  Amazon Development Centre Canada ULC

  8+ YOECandidates need a bachelor's degree in electrical engineering or a related field and 8+ years of constrained-random verification experience (such as UVM), including testbench development. Experience across IP, SoC and full-system verification, plus formal, emulation or scripting skills, is highly desired.

  UVM, formal verification tools, emulation platforms, Python, Perl

• 1mo

  Principal Design Verification Engineer

  Toronto, ON

  

  indie

  7+ YOECandidates need a BSEE, BSCE or BSCS and 7+ years of design verification experience. Required skills include constrained random verification with SystemVerilog and UVM, coverage-driven verification, and strong programming in C/C++ with Python, Tcl or Perl scripting.

  SystemVerilog, UVM, C, C++, Python, Tcl

8 companies