ASICS Design Verification Engineer (Vancouver, Markham OR Remote)
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in engineering or science and 2+ years of ASIC design or verification experience. Preferred skills include SystemVerilog and UVM testbench development, RTL design, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python