ASIC Digital Design, Sr Staff Engineer-19314
Markham, ONS
Synopsys
8+ YOECandidates need a BS or MS in electronics or electrical engineering with 8+ years of digital verification experience in VMM or UVM. Strong Verilog and SystemVerilog testbench skills, debugging ability, and familiarity with Python or Perl are required.
Verilog, SystemVerilog, UVM, VMM, Jira, Confluence
Hardware Engineering, Staff Engineer- 19028
Nepean, ONS
Synopsys
Candidates need proven experience with high-speed interface signaling, signal and power integrity analysis, and EDA tools such as HFSS, Ansys, HSPICE, Raptor and ADS. They also need strong communication skills and board-level and on-chip IO design knowledge.
HFSS, Ansys, HSPICE, Raptor, ADS