Senior ASIC Design Engineer - Client IP
Ottawa, ON$112k–$179k/yrFull Time
CC
Ciena Canada ULC
5+ YOECandidates need an engineering degree at the bachelor or master level and 5+ years of SystemVerilog design and digital synthesis, timing closure and clock-crossing experience. Strong independent problem solving, English communication, and knowledge of verification and timing/power/area trade-offs are required.
Git, Jira, Python, Make, bash
ASIC Front End Implementation Engineer
Ottawa, ONFull Time
CC
Ciena Canada ULC
5+ YOECandidates need a B.Sc. in electrical or computer engineering and 5+ years of ASIC digital design and DFT experience. They must have hands-on DFT and synthesis tool skills and be able to work well in engineering teams.
Synthesis tools, Static timing analysis tools, DFT tools, EDA tools